Searched refs:getRegBitWidth (Results 1 – 11 of 11) sorted by relevance
94 uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub)); in mask()271 assert(getRegBitWidth(Reg[N]) == W && "Register width mismatch"); in evaluate()311 uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(Reg[0]) : 0; in evaluate()369 uint16_t W1 = getRegBitWidth(Reg[1]); in evaluate()703 uint16_t W1 = getRegBitWidth(Reg[1]); in evaluate()758 assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32); in evaluate()770 assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32); in evaluate()832 uint16_t W1 = getRegBitWidth(Reg[1]); in evaluate()864 uint16_t W1 = getRegBitWidth(Reg[1]); in evaluate()969 uint16_t RW = getRegBitWidth(PD); in evaluate()[all …]
329 uint16_t BT::MachineEvaluator::getRegBitWidth(const RegisterRef &RR) const { in getRegBitWidth() function in BT::MachineEvaluator350 uint16_t BW = getRegBitWidth(RR); in getCell()709 uint16_t W = getRegBitWidth(Reg); in mask()733 uint16_t W = getRegBitWidth(RD); in evaluate()747 uint16_t WD = getRegBitWidth(RD); in evaluate()748 uint16_t WS = getRegBitWidth(RS); in evaluate()805 uint16_t DefBW = ME.getRegBitWidth(DefRR); in visitPHI()882 uint16_t DefBW = ME.getRegBitWidth(RD); in visitNonBranch()
1855 unsigned getRegBitWidth(unsigned Reg) const;1992 unsigned W = getRegBitWidth(DefR.Reg); in evaluate()2153 unsigned BW = getRegBitWidth(R1.Reg); in evaluate()2360 unsigned HexagonConstEvaluator::getRegBitWidth(unsigned Reg) const { in getRegBitWidth() function in HexagonConstEvaluator2698 unsigned W = getRegBitWidth(DefR.Reg); in evaluateHexCondMove()2752 unsigned BW = getRegBitWidth(DefR.Reg); in evaluateHexExt()2901 unsigned W = getRegBitWidth(R); in rewriteHexConstDefs()
397 uint16_t getRegBitWidth(const RegisterRef &RR) const;
1160 unsigned getRegBitWidth(unsigned RCID);1163 unsigned getRegBitWidth(const MCRegisterClass &RC);
2208 unsigned getRegBitWidth(unsigned RCID) { in getRegBitWidth() function2349 unsigned getRegBitWidth(const MCRegisterClass &RC) { in getRegBitWidth() function2350 return getRegBitWidth(RC.getID()); in getRegBitWidth()2357 return getRegBitWidth(MRI->getRegClass(RCID)) / 8; in getRegOperandSize()
833 if (AMDGPU::getRegBitWidth(VDataRCID) > 64 && in createsVALUHazard()845 AMDGPU::getRegBitWidth(Desc.operands()[SRsrcIdx].RegClass) == 256); in createsVALUHazard()851 if (AMDGPU::getRegBitWidth(Desc.operands()[DataIdx].RegClass) > 64) in createsVALUHazard()
896 if (UseOp.getSubReg() && AMDGPU::getRegBitWidth(FoldRC->getID()) == 64) { in foldOperand()900 if (AMDGPU::getRegBitWidth(UseRC->getID()) != 64) in foldOperand()
1329 const unsigned RegWidth = AMDGPU::getRegBitWidth(RC->getID()) / 8; in buildSpillLoadStore()2886 const unsigned RegBitWidth = AMDGPU::getRegBitWidth(*RC->MC); in getRegSplitParts()
2861 int NumInsts = AMDGPU::getRegBitWidth(RC->getID()) / 32; in canInsertSelect()2876 int NumInsts = AMDGPU::getRegBitWidth(RC->getID()) / 32; in canInsertSelect()
762 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID)); in printRegularOperand()