Home
last modified time | relevance | path

Searched refs:gfxclk_pstate (Results 1 – 11 of 11) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_6_ppt.c619 pstate_table->gfxclk_pstate.standard = in smu_v13_0_6_populate_umd_state_clk()
626 pstate_table->gfxclk_pstate.standard = in smu_v13_0_6_populate_umd_state_clk()
627 pstate_table->gfxclk_pstate.min; in smu_v13_0_6_populate_umd_state_clk()
1579 pstate_table->gfxclk_pstate.custom.min = in smu_v13_0_6_usr_edit_dpm_table()
1580 pstate_table->gfxclk_pstate.curr.min; in smu_v13_0_6_usr_edit_dpm_table()
1592 pstate_table->gfxclk_pstate.custom.max = in smu_v13_0_6_usr_edit_dpm_table()
1593 pstate_table->gfxclk_pstate.curr.max; in smu_v13_0_6_usr_edit_dpm_table()
1623 pstate_table->gfxclk_pstate.custom.min = in smu_v13_0_6_usr_edit_dpm_table()
1624 pstate_table->gfxclk_pstate.curr.min; in smu_v13_0_6_usr_edit_dpm_table()
1627 pstate_table->gfxclk_pstate.custom.max = in smu_v13_0_6_usr_edit_dpm_table()
[all …]
H A Daldebaran_ppt.c538 pstate_table->gfxclk_pstate.standard = in aldebaran_populate_umd_state_clk()
545 pstate_table->gfxclk_pstate.standard = in aldebaran_populate_umd_state_clk()
546 pstate_table->gfxclk_pstate.min; in aldebaran_populate_umd_state_clk()
1398 pstate_table->gfxclk_pstate.custom.min = in aldebaran_usr_edit_dpm_table()
1399 pstate_table->gfxclk_pstate.curr.min; in aldebaran_usr_edit_dpm_table()
1408 pstate_table->gfxclk_pstate.custom.max = in aldebaran_usr_edit_dpm_table()
1409 pstate_table->gfxclk_pstate.curr.max; in aldebaran_usr_edit_dpm_table()
1436 pstate_table->gfxclk_pstate.custom.min = in aldebaran_usr_edit_dpm_table()
1437 pstate_table->gfxclk_pstate.curr.min; in aldebaran_usr_edit_dpm_table()
1440 pstate_table->gfxclk_pstate.custom.max = in aldebaran_usr_edit_dpm_table()
[all …]
H A Dsmu_v13_0_7_ppt.c1855 pstate_table->gfxclk_pstate.min = gfx_table->min; in smu_v13_0_7_populate_umd_state_clk()
1858 pstate_table->gfxclk_pstate.peak = driver_clocks.GameClockAc; in smu_v13_0_7_populate_umd_state_clk()
1860 pstate_table->gfxclk_pstate.peak = gfx_table->max; in smu_v13_0_7_populate_umd_state_clk()
1879 pstate_table->gfxclk_pstate.standard = driver_clocks.BaseClockAc; in smu_v13_0_7_populate_umd_state_clk()
1881 pstate_table->gfxclk_pstate.standard = gfx_table->max; in smu_v13_0_7_populate_umd_state_clk()
H A Dsmu_v13_0.c1752 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard; in smu_v13_0_set_performance_level()
1760 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min; in smu_v13_0_set_performance_level()
1766 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak; in smu_v13_0_set_performance_level()
1801 pstate_table->gfxclk_pstate.curr.min = sclk_min; in smu_v13_0_set_performance_level()
1802 pstate_table->gfxclk_pstate.curr.max = sclk_max; in smu_v13_0_set_performance_level()
H A Dsmu_v13_0_0_ppt.c1879 pstate_table->gfxclk_pstate.min = gfx_table->min; in smu_v13_0_0_populate_umd_state_clk()
1882 pstate_table->gfxclk_pstate.peak = driver_clocks.GameClockAc; in smu_v13_0_0_populate_umd_state_clk()
1884 pstate_table->gfxclk_pstate.peak = gfx_table->max; in smu_v13_0_0_populate_umd_state_clk()
1903 pstate_table->gfxclk_pstate.standard = driver_clocks.BaseClockAc; in smu_v13_0_0_populate_umd_state_clk()
1905 pstate_table->gfxclk_pstate.standard = gfx_table->max; in smu_v13_0_0_populate_umd_state_clk()
/openbsd/sys/dev/pci/drm/amd/pm/swsmu/smu11/
H A Darcturus_ppt.c542 pstate_table->gfxclk_pstate.min = gfx_table->min; in arcturus_populate_umd_state_clk()
543 pstate_table->gfxclk_pstate.peak = gfx_table->max; in arcturus_populate_umd_state_clk()
554 pstate_table->gfxclk_pstate.standard = in arcturus_populate_umd_state_clk()
561 pstate_table->gfxclk_pstate.standard = in arcturus_populate_umd_state_clk()
562 pstate_table->gfxclk_pstate.min; in arcturus_populate_umd_state_clk()
H A Dsmu_v11_0.c1872 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard; in smu_v11_0_set_performance_level()
1877 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min; in smu_v11_0_set_performance_level()
1883 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak; in smu_v11_0_set_performance_level()
H A Dnavi10_ppt.c1714 pstate_table->gfxclk_pstate.min = gfx_table->min; in navi10_populate_umd_state_clk()
1761 pstate_table->gfxclk_pstate.peak = sclk_freq; in navi10_populate_umd_state_clk()
1772 pstate_table->gfxclk_pstate.standard = in navi10_populate_umd_state_clk()
1779 pstate_table->gfxclk_pstate.standard = in navi10_populate_umd_state_clk()
1780 pstate_table->gfxclk_pstate.min; in navi10_populate_umd_state_clk()
H A Dsienna_cichlid_ppt.c1488 pstate_table->gfxclk_pstate.min = gfx_table->min; in sienna_cichlid_populate_umd_state_clk()
1489 pstate_table->gfxclk_pstate.peak = gfx_table->max; in sienna_cichlid_populate_umd_state_clk()
1500 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK; in sienna_cichlid_populate_umd_state_clk()
1505 pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK; in sienna_cichlid_populate_umd_state_clk()
1510 pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK; in sienna_cichlid_populate_umd_state_clk()
/openbsd/sys/dev/pci/drm/amd/pm/swsmu/inc/
H A Damdgpu_smu.h443 struct pstates_clk_freq gfxclk_pstate; member
/openbsd/sys/dev/pci/drm/amd/pm/swsmu/
H A Damdgpu_smu.c2560 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; in smu_read_sensor()
2568 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; in smu_read_sensor()