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Searched refs:hw_crtc_timing (Results 1 – 8 of 8) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/display/dc/dcn31/
H A Ddcn31_hpo_dp_stream_encoder.c216 if (hw_crtc_timing.flags.INTERLACE) { in dcn31_hpo_dp_stream_enc_set_stream_attribute()
230 switch (hw_crtc_timing.pixel_encoding) { in dcn31_hpo_dp_stream_enc_set_stream_attribute()
239 if (hw_crtc_timing.flags.Y_ONLY) { in dcn31_hpo_dp_stream_enc_set_stream_attribute()
346 h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left - in dcn31_hpo_dp_stream_enc_set_stream_attribute()
347 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right; in dcn31_hpo_dp_stream_enc_set_stream_attribute()
350 hw_crtc_timing.h_sync_width; in dcn31_hpo_dp_stream_enc_set_stream_attribute()
355 v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top - in dcn31_hpo_dp_stream_enc_set_stream_attribute()
356 hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom - in dcn31_hpo_dp_stream_enc_set_stream_attribute()
357 hw_crtc_timing.v_front_porch; in dcn31_hpo_dp_stream_enc_set_stream_attribute()
359 …h_width = hw_crtc_timing.h_border_left + hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_ri… in dcn31_hpo_dp_stream_enc_set_stream_attribute()
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/openbsd/sys/dev/pci/drm/amd/display/dc/dce/
H A Ddce_stream_encoder.c289 hw_crtc_timing.v_total /= 2; in dce110_stream_encoder_dp_set_stream_attribute()
462 h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left - in dce110_stream_encoder_dp_set_stream_attribute()
463 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right; in dce110_stream_encoder_dp_set_stream_attribute()
466 hw_crtc_timing.h_sync_width; in dce110_stream_encoder_dp_set_stream_attribute()
472 v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top - in dce110_stream_encoder_dp_set_stream_attribute()
473 hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom - in dce110_stream_encoder_dp_set_stream_attribute()
474 hw_crtc_timing.v_front_porch; in dce110_stream_encoder_dp_set_stream_attribute()
486 hw_crtc_timing.h_sync_width, in dce110_stream_encoder_dp_set_stream_attribute()
490 hw_crtc_timing.v_sync_width, in dce110_stream_encoder_dp_set_stream_attribute()
498 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right, in dce110_stream_encoder_dp_set_stream_attribute()
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/openbsd/sys/dev/pci/drm/amd/display/dc/dcn10/
H A Ddcn10_stream_encoder.c268 hw_crtc_timing.v_total /= 2; in enc1_stream_encoder_dp_set_stream_attribute()
427 h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left - in enc1_stream_encoder_dp_set_stream_attribute()
428 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right; in enc1_stream_encoder_dp_set_stream_attribute()
431 hw_crtc_timing.h_sync_width; in enc1_stream_encoder_dp_set_stream_attribute()
437 v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top - in enc1_stream_encoder_dp_set_stream_attribute()
438 hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom - in enc1_stream_encoder_dp_set_stream_attribute()
439 hw_crtc_timing.v_front_porch; in enc1_stream_encoder_dp_set_stream_attribute()
449 hw_crtc_timing.h_sync_width, in enc1_stream_encoder_dp_set_stream_attribute()
453 hw_crtc_timing.v_sync_width, in enc1_stream_encoder_dp_set_stream_attribute()
460 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right, in enc1_stream_encoder_dp_set_stream_attribute()
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H A Ddcn10_optc.c1303 struct dc_crtc_timing *hw_crtc_timing) in optc1_get_hw_timing() argument
1307 if (tg == NULL || hw_crtc_timing == NULL) in optc1_get_hw_timing()
1312 hw_crtc_timing->h_total = s.h_total + 1; in optc1_get_hw_timing()
1313 hw_crtc_timing->h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end); in optc1_get_hw_timing()
1314 hw_crtc_timing->h_front_porch = s.h_total + 1 - s.h_blank_start; in optc1_get_hw_timing()
1315 hw_crtc_timing->h_sync_width = s.h_sync_a_end - s.h_sync_a_start; in optc1_get_hw_timing()
1317 hw_crtc_timing->v_total = s.v_total + 1; in optc1_get_hw_timing()
1318 hw_crtc_timing->v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end); in optc1_get_hw_timing()
1319 hw_crtc_timing->v_front_porch = s.v_total + 1 - s.v_blank_start; in optc1_get_hw_timing()
1320 hw_crtc_timing->v_sync_width = s.v_sync_a_end - s.v_sync_a_start; in optc1_get_hw_timing()
H A Ddcn10_hw_sequencer.c2113 struct dc_crtc_timing *hw_crtc_timing; in dcn10_align_pixel_clocks() local
2124 hw_crtc_timing = kcalloc(MAX_PIPES, sizeof(*hw_crtc_timing), GFP_KERNEL); in dcn10_align_pixel_clocks()
2125 if (!hw_crtc_timing) in dcn10_align_pixel_clocks()
2140 &hw_crtc_timing[i]); in dcn10_align_pixel_clocks()
2145 hw_crtc_timing[i].pix_clk_100hz = pclk; in dcn10_align_pixel_clocks()
2155 hw_crtc_timing[i].h_total* in dcn10_align_pixel_clocks()
2156 hw_crtc_timing[i].v_total; in dcn10_align_pixel_clocks()
2192 kfree(hw_crtc_timing); in dcn10_align_pixel_clocks()
H A Ddcn10_optc.h626 struct dc_crtc_timing *hw_crtc_timing);
/openbsd/sys/dev/pci/drm/amd/display/dc/core/
H A Damdgpu_dc.c1580 struct dc_crtc_timing hw_crtc_timing = {0}; in dc_validate_boot_timing() local
1628 if (!tg->funcs->get_hw_timing(tg, &hw_crtc_timing)) in dc_validate_boot_timing()
1631 if (crtc_timing->h_total != hw_crtc_timing.h_total) in dc_validate_boot_timing()
1634 if (crtc_timing->h_border_left != hw_crtc_timing.h_border_left) in dc_validate_boot_timing()
1637 if (crtc_timing->h_addressable != hw_crtc_timing.h_addressable) in dc_validate_boot_timing()
1646 if (crtc_timing->h_sync_width != hw_crtc_timing.h_sync_width) in dc_validate_boot_timing()
1649 if (crtc_timing->v_total != hw_crtc_timing.v_total) in dc_validate_boot_timing()
1652 if (crtc_timing->v_border_top != hw_crtc_timing.v_border_top) in dc_validate_boot_timing()
1664 if (crtc_timing->v_sync_width != hw_crtc_timing.v_sync_width) in dc_validate_boot_timing()
1699 &hw_crtc_timing.pixel_encoding, in dc_validate_boot_timing()
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/openbsd/sys/dev/pci/drm/amd/display/dc/inc/hw/
H A Dtiming_generator.h293 struct dc_crtc_timing *hw_crtc_timing);