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Searched refs:hw_ops (Results 1 – 25 of 36) sorted by relevance

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/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dmca_v3_0.c61 .hw_ops = &mca_v3_0_mp0_hw_ops,
81 .hw_ops = &mca_v3_0_mp1_hw_ops,
101 .hw_ops = &mca_v3_0_mpio_hw_ops,
H A Damdgpu_ras.c1039 if (!block_obj || !block_obj->hw_ops) { in amdgpu_ras_query_error_status()
1114 if (!block_obj || !block_obj->hw_ops) { in amdgpu_ras_reset_error_status()
1120 if (block_obj->hw_ops->reset_ras_error_count) in amdgpu_ras_reset_error_status()
1156 if (!block_obj || !block_obj->hw_ops) { in amdgpu_ras_error_inject()
1170 if (block_obj->hw_ops->ras_error_inject) { in amdgpu_ras_error_inject()
1700 if (block_obj->hw_ops && block_obj->hw_ops->query_poison_status) { in amdgpu_ras_interrupt_poison_consumption_handler()
1713 if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption) in amdgpu_ras_interrupt_poison_consumption_handler()
1968 if (!block_obj || !block_obj->hw_ops) { in amdgpu_ras_error_status_query()
2802 if (ras_obj->ras_cb || (ras_obj->hw_ops && in amdgpu_ras_block_late_init()
2803 (ras_obj->hw_ops->query_poison_status || in amdgpu_ras_block_late_init()
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H A Damdgpu_umc.c91 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_do_page_retirement()
92 adev->umc.ras->ras_block.hw_ops->query_ras_error_count) in amdgpu_umc_do_page_retirement()
93 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, ras_error_status); in amdgpu_umc_do_page_retirement()
95 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_do_page_retirement()
96 adev->umc.ras->ras_block.hw_ops->query_ras_error_address && in amdgpu_umc_do_page_retirement()
112 adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, ras_error_status); in amdgpu_umc_do_page_retirement()
H A Dhdp_v4_0.c164 .hw_ops = &hdp_v4_0_ras_hw_ops,
H A Dsdma_v4_4.c272 .hw_ops = &sdma_v4_4_ras_hw_ops,
H A Dgmc_v9_0.c1658 if (adev->mmhub.ras && adev->mmhub.ras->ras_block.hw_ops && in gmc_v9_0_late_init()
1659 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count) in gmc_v9_0_late_init()
1660 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(adev); in gmc_v9_0_late_init()
1662 if (adev->hdp.ras && adev->hdp.ras->ras_block.hw_ops && in gmc_v9_0_late_init()
1663 adev->hdp.ras->ras_block.hw_ops->reset_ras_error_count) in gmc_v9_0_late_init()
1664 adev->hdp.ras->ras_block.hw_ops->reset_ras_error_count(adev); in gmc_v9_0_late_init()
H A Damdgpu_xgmi.c915 adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev); in amdgpu_xgmi_ras_late_init()
1081 adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev); in amdgpu_xgmi_query_ras_error_count()
1123 .hw_ops = &xgmi_ras_hw_ops,
H A Dumc_v6_1.c459 .hw_ops = &umc_v6_1_ras_hw_ops,
H A Damdgpu_gfx.c880 if (adev->gfx.ras && adev->gfx.ras->ras_block.hw_ops && in amdgpu_gfx_process_ras_data_cb()
881 adev->gfx.ras->ras_block.hw_ops->query_ras_error_count) in amdgpu_gfx_process_ras_data_cb()
882 adev->gfx.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data); in amdgpu_gfx_process_ras_data_cb()
H A Dsdma_v4_4_2.c1282 if (adev->sdma.ras && adev->sdma.ras->ras_block.hw_ops && in sdma_v4_4_2_late_init()
1283 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count) in sdma_v4_4_2_late_init()
1284 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count(adev); in sdma_v4_4_2_late_init()
2184 .hw_ops = &sdma_v4_4_2_ras_hw_ops,
H A Dumc_v8_7.c441 .hw_ops = &umc_v8_7_ras_hw_ops,
H A Dumc_v8_10.c459 .hw_ops = &umc_v8_10_ras_hw_ops,
H A Dumc_v6_7.c523 .hw_ops = &umc_v6_7_ras_hw_ops,
H A Damdgpu_ras.h556 const struct amdgpu_ras_block_hw_ops *hw_ops; member
H A Dsdma_v4_0.c1752 if (adev->sdma.ras && adev->sdma.ras->ras_block.hw_ops && in sdma_v4_0_late_init()
1753 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count) in sdma_v4_0_late_init()
1754 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count(adev); in sdma_v4_0_late_init()
2621 .hw_ops = &sdma_v4_0_ras_hw_ops,
H A Dnbio_v7_9.c735 .hw_ops = &nbio_v7_9_ras_hw_ops,
H A Djpeg_v2_5.c818 .hw_ops = &jpeg_v2_6_ras_hw_ops,
H A Djpeg_v4_0.c827 .hw_ops = &jpeg_v4_0_ras_hw_ops,
H A Dnbio_v7_4.c666 .hw_ops = &nbio_v7_4_ras_hw_ops,
H A Damdgpu_device.c3432 if (adev->mmhub.ras && adev->mmhub.ras->ras_block.hw_ops && in amdgpu_device_xgmi_reset_func()
3433 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count) in amdgpu_device_xgmi_reset_func()
3434 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(adev); in amdgpu_device_xgmi_reset_func()
5112 if (tmp_adev->mmhub.ras && tmp_adev->mmhub.ras->ras_block.hw_ops && in amdgpu_do_asic_reset()
5113 tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count) in amdgpu_do_asic_reset()
5114 tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(tmp_adev); in amdgpu_do_asic_reset()
H A Dmmhub_v1_0.c787 .hw_ops = &mmhub_v1_0_ras_hw_ops,
H A Dmmhub_v1_8.c842 .hw_ops = &mmhub_v1_8_ras_hw_ops,
H A Dgfx_v9_4.c1017 .hw_ops = &gfx_v9_4_ras_ops,
H A Djpeg_v4_0_3.c1217 .hw_ops = &jpeg_v4_0_3_ras_hw_ops,
/openbsd/sys/dev/ic/
H A Dqwx.c1858 if (sc->hw_params.hw_ops->get_hw_mac_from_pdev_id) in qwx_hw_get_mac_from_pdev_id()
3385 .hw_ops = &ipq8074_ops,
3477 .hw_ops = &ipq6018_ops,
3566 .hw_ops = &qca6390_ops,
3660 .hw_ops = &qcn9074_ops,
3747 .hw_ops = &wcn6855_ops,
3838 .hw_ops = &wcn6855_ops,
3928 .hw_ops = &wcn6750_ops,
10399 sc->hw_params.hw_ops->reo_setup(sc); in qwx_dp_srng_common_setup()
18985 sc->hw_params.hw_ops->wmi_init_config(sc, &config); in qwx_wmi_cmd_init()
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