| /openbsd/sys/dev/pci/drm/amd/display/dc/dce/ |
| H A D | dce_hwseq.c | 32 hws->ctx
34 hws->regs->reg
38 hws->shifts->field_name, hws->masks->field_name
40 void dce_enable_fe_clock(struct dce_hwseq *hws, in dce_enable_fe_clock() argument
53 struct dce_hwseq *hws = dc->hwseq; in dce_pipe_control_lock() local
75 if (hws->masks->BLND_BLND_V_UPDATE_LOCK != 0) in dce_pipe_control_lock()
80 if (hws->wa.blnd_crtc_trigger) { in dce_pipe_control_lock()
97 void dce_set_blender_mode(struct dce_hwseq *hws, in dce_set_blender_mode() argument
129 if (hws->masks->BLND_ALPHA_MODE != 0) { in dce_set_blender_mode()
170 dce_disable_sram_shut_down(hws); in dce_clock_gating_power_up()
[all …]
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn303/ |
| H A D | dcn303_hwseq.c | 18 hws->ctx
20 hws->regs->reg
24 hws->shifts->field_name, hws->masks->field_name
27 void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on) in dcn303_dpp_pg_control() argument
32 void dcn303_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) in dcn303_hubp_pg_control() argument
37 void dcn303_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on) in dcn303_dsc_pg_control() argument
42 void dcn303_enable_power_gating_plane(struct dce_hwseq *hws, bool enable) in dcn303_enable_power_gating_plane() argument
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| H A D | dcn303_hwseq.h | 13 void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);
14 void dcn303_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
15 void dcn303_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on);
16 void dcn303_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);
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| /openbsd/sys/dev/pci/drm/i915/selftests/ |
| H A D | igt_spinner.c | 22 if (IS_ERR(spin->hws)) { in igt_spinner_init()
23 err = PTR_ERR(spin->hws); in igt_spinner_init()
37 i915_gem_object_put(spin->hws); in igt_spinner_init()
129 struct i915_vma *hws, *vma; in igt_spinner_create_request() local
145 hws = spin->hws_vma; in igt_spinner_create_request()
164 *batch++ = lower_32_bits(hws_address(hws, rq)); in igt_spinner_create_request()
169 *batch++ = hws_address(hws, rq); in igt_spinner_create_request()
173 *batch++ = hws_address(hws, rq); in igt_spinner_create_request()
176 *batch++ = hws_address(hws, rq); in igt_spinner_create_request()
245 i915_gem_object_unpin_map(spin->hws); in igt_spinner_fini()
[all …]
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn31/ |
| H A D | dcn31_hwseq.c | 57 hws->ctx
59 hws->regs->reg
66 hws->shifts->field_name, hws->masks->field_name
70 struct dce_hwseq *hws = dc->hwseq; in enable_memory_low_power() local
111 struct dce_hwseq *hws = dc->hwseq; in dcn31_init_hw() local
121 hws->funcs.bios_golden_init(dc); in dcn31_init_hw()
122 if (hws->funcs.disable_vga) in dcn31_init_hw()
123 hws->funcs.disable_vga(dc->hwseq); in dcn31_init_hw()
243 hws->funcs.setup_hpo_hw_control(hws, false); in dcn31_init_hw()
278 struct dce_hwseq *hws, in dcn31_dsc_pg_control() argument
[all …]
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| H A D | dcn31_hwseq.h | 36 struct dce_hwseq *hws,
41 struct dce_hwseq *hws,
49 void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
50 int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_co…
57 void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn302/ |
| H A D | dcn302_hwseq.c | 36 hws->ctx
38 hws->regs->reg
42 hws->shifts->field_name, hws->masks->field_name
45 void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on) in dcn302_dpp_pg_control() argument
50 if (hws->ctx->dc->debug.disable_dpp_power_gate) in dcn302_dpp_pg_control()
102 void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) in dcn302_hubp_pg_control() argument
107 if (hws->ctx->dc->debug.disable_hubp_power_gate) in dcn302_hubp_pg_control()
159 void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on) in dcn302_dsc_pg_control() argument
165 if (hws->ctx->dc->debug.disable_dsc_power_gate) in dcn302_dsc_pg_control()
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| H A D | dcn302_hwseq.h | 31 void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);
32 void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
33 void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on);
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn201/ |
| H A D | dcn201_hwseq.c | 44 hws->ctx
47 hws->regs->reg
54 hws->shifts->field_name, hws->masks->field_name
209 hws->fb_base.low_part = fb_base; in read_mmhub_vm_setup()
210 hws->fb_base.quad_part <<= 24; in read_mmhub_vm_setup()
212 hws->fb_top.low_part = fb_top; in read_mmhub_vm_setup()
213 hws->fb_top.quad_part <<= 24; in read_mmhub_vm_setup()
215 hws->fb_offset.quad_part <<= 24; in read_mmhub_vm_setup()
217 hws->uma_top.quad_part = hws->fb_top.quad_part in read_mmhub_vm_setup()
218 - hws->fb_base.quad_part + hws->fb_offset.quad_part; in read_mmhub_vm_setup()
[all …]
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn314/ |
| H A D | dcn314_hwseq.c | 61 hws->ctx
63 hws->regs->reg
70 hws->shifts->field_name, hws->masks->field_name
238 struct dce_hwseq *hws, in dcn314_dsc_pg_control() argument
246 if (hws->ctx->dc->debug.disable_dsc_power_gate) in dcn314_dsc_pg_control()
250 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc && in dcn314_dsc_pg_control()
252 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc( in dcn314_dsc_pg_control()
253 hws->ctx->dc->res_pool->dccg, dsc_inst); in dcn314_dsc_pg_control()
302 hws->ctx->dc->res_pool->dccg->funcs->disable_dsc( in dcn314_dsc_pg_control()
303 hws->ctx->dc->res_pool->dccg, dsc_inst); in dcn314_dsc_pg_control()
[all …]
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| H A D | dcn314_hwseq.h | 36 void dcn314_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on);
38 void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);
44 void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context);
46 void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);
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| /openbsd/sys/dev/pci/drm/amd/display/dc/inc/ |
| H A D | hw_sequencer_private.h | 110 void (*disable_vga)(struct dce_hwseq *hws);
116 void (*enable_power_gating_plane)(struct dce_hwseq *hws,
119 struct dce_hwseq *hws,
122 void (*dpp_pg_control)(struct dce_hwseq *hws,
125 void (*hubp_pg_control)(struct dce_hwseq *hws,
128 void (*dsc_pg_control)(struct dce_hwseq *hws,
131 bool (*dsc_pg_status)(struct dce_hwseq *hws,
145 void (*dccg_init)(struct dce_hwseq *hws);
154 void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable);
163 void (*resync_fifo_dccg_dio)(struct dce_hwseq *hws, struct dc *dc,
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_hwseq.h | 91 struct dce_hwseq *hws);
94 struct dce_hwseq *hws,
97 struct dce_hwseq *hws,
101 struct dce_hwseq *hws,
120 struct dce_hwseq *hws,
128 struct dce_hwseq *hws,
134 void dcn20_dccg_init(struct dce_hwseq *hws);
135 int dcn20_init_sys_ctx(struct dce_hwseq *hws,
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| H A D | dcn20_hwseq.c | 62 hws->ctx
64 hws->regs->reg
68 hws->shifts->field_name, hws->masks->field_name
189 struct dce_hwseq *hws, in dcn20_enable_power_gating_plane() argument
263 struct dce_hwseq *hws) in dcn20_disable_vga() argument
1131 hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true); in dcn20_power_on_plane_resources()
1134 hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true); in dcn20_power_on_plane_resources()
2286 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true); in dcn20_disable_stream_gating()
2288 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true); in dcn20_disable_stream_gating()
2824 hws->funcs.enable_power_gating_plane(hws, true); in dcn20_fpga_init_hw()
[all …]
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn301/ |
| H A D | dcn301_hwseq.c | 34 hws->ctx
36 hws->regs->reg
40 hws->shifts->field_name, hws->masks->field_name
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_hw_sequencer.c | 63 hws->ctx
65 hws->regs->reg
69 hws->shifts->field_name, hws->masks->field_name
737 hws->funcs.dpp_root_clock_control(hws, plane_id, true); in power_on_plane_resources()
744 hws->funcs.dpp_pg_control(hws, plane_id, true); in power_on_plane_resources()
747 hws->funcs.hubp_pg_control(hws, plane_id, true); in power_on_plane_resources()
769 hws->funcs.hubp_pg_control(hws, 0, false); in undo_DEGVIDCN10_253_wa()
798 hws->funcs.hubp_pg_control(hws, 0, true); in apply_DEGVIDCN10_253_wa()
1238 hws->funcs.dpp_pg_control(hws, dpp->inst, false); in dcn10_plane_atomic_power_down()
1241 hws->funcs.hubp_pg_control(hws, hubp->inst, false); in dcn10_plane_atomic_power_down()
[all …]
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| H A D | dcn10_hw_sequencer.h | 87 struct dce_hwseq *hws,
91 struct dce_hwseq *hws,
95 struct dce_hwseq *hws,
99 struct dce_hwseq *hws);
112 void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data);
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn32/ |
| H A D | dcn32_hwseq.h | 34 struct dce_hwseq *hws,
39 struct dce_hwseq *hws,
42 void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
78 void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context);
105 struct dce_hwseq *hws,
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| H A D | dcn32_hwseq.c | 57 hws->ctx
59 hws->regs->reg
66 hws->shifts->field_name, hws->masks->field_name
69 struct dce_hwseq *hws, in dcn32_dsc_pg_control() argument
131 struct dce_hwseq *hws, in dcn32_enable_power_gating_plane() argument
556 hws->funcs.set_mcm_luts) in dcn32_set_input_transfer_func()
714 if (hws && hws->funcs.update_mall_sel) in dcn32_program_mall_pipe_config()
1406 struct dce_hwseq *hws, in dcn32_dsc_pg_status() argument
1446 bool is_dsc_ungated = hws->funcs.dsc_pg_status(hws, dsc->inst); in dcn32_update_dsc_pg()
1450 hws->funcs.dsc_pg_control(hws, dsc->inst, true); in dcn32_update_dsc_pg()
[all …]
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dce120/ |
| H A D | dce120_hw_sequencer.c | 41 hws->ctx
43 hws->regs->reg
47 hws->shifts->field_name, hws->masks->field_name
194 struct dce_hwseq *hws, in dce120_update_dchub() argument
250 bool dce121_xgmi_enabled(struct dce_hwseq *hws) in dce121_xgmi_enabled() argument
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| H A D | dce120_resource.c | 807 if (hws) { in dce120_hwseq_create()
808 hws->ctx = ctx; in dce120_hwseq_create()
809 hws->regs = &hwseq_reg; in dce120_hwseq_create()
810 hws->shifts = &hwseq_shift; in dce120_hwseq_create()
811 hws->masks = &hwseq_mask; in dce120_hwseq_create()
813 return hws; in dce120_hwseq_create()
821 if (hws) { in dce121_hwseq_create()
822 hws->ctx = ctx; in dce121_hwseq_create()
823 hws->regs = &dce121_hwseq_reg; in dce121_hwseq_create()
825 hws->masks = &dce121_hwseq_mask; in dce121_hwseq_create()
[all …]
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn21/ |
| H A D | dcn21_hwseq.c | 43 hws->ctx
45 hws->regs->reg
49 hws->shifts->field_name, hws->masks->field_name
53 struct dce_hwseq *hws) in mmhub_update_page_table_config() argument
67 int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_co… in dcn21_init_sys_ctx() argument
81 mmhub_update_page_table_config(&config, hws); in dcn21_init_sys_ctx()
90 struct dce_hwseq *hws = dc->hwseq; in dcn21_s0i3_golden_init_wa() local
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| /openbsd/sys/dev/pci/drm/i915/gt/ |
| H A D | selftest_hangcheck.c | 34 struct drm_i915_gem_object *hws; member
56 if (IS_ERR(h->hws)) { in hang_init()
57 err = PTR_ERR(h->hws); in hang_init()
90 i915_gem_object_put(h->hws); in hang_init()
99 return i915_vma_offset(hws) + in hws_address()
110 struct i915_vma *hws, *vma; in hang_create_request() local
141 hws = i915_vma_instance(h->hws, vm, NULL); in hang_create_request()
142 if (IS_ERR(hws)) { in hang_create_request()
144 return ERR_CAST(hws); in hang_create_request()
246 i915_vma_unpin(hws); in hang_create_request()
[all …]
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dce110/ |
| H A D | dce110_hw_sequencer.c | 83 hws->ctx
88 hws->regs->reg
92 hws->shifts->field_name, hws->masks->field_name
1486 struct dce_hwseq *hws = dc->hwseq; in apply_single_controller_ctx_to_hw() local
1740 struct dce_hwseq *hws = dc->hwseq; in dce110_enable_accelerated_mode() local
1754 if (hws->funcs.init_pipes) in dce110_enable_accelerated_mode()
2240 struct dce_hwseq *hws = dc->hwseq; in dce110_apply_ctx_to_hw() local
2315 hws->funcs.resync_fifo_dccg_dio(hws, dc, context); in dce110_apply_ctx_to_hw()
2590 struct dce_hwseq *hws = dc->hwseq; in init_hw() local
2696 struct dce_hwseq *hws = dc->hwseq; in dce110_program_front_end_for_pipe() local
[all …]
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_hwseq.c | 61 hws->ctx
63 hws->regs->reg
70 hws->shifts->field_name, hws->masks->field_name
150 struct dce_hwseq *hws = dc->hwseq; in dcn30_set_input_transfer_func() local
180 hws->funcs.set_blend_lut(pipe_ctx, plane_state); in dcn30_set_input_transfer_func()
183 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state); in dcn30_set_input_transfer_func()
432 struct dce_hwseq *hws = dc->hwseq; in dcn30_init_hw() local
447 hws->funcs.bios_golden_init(dc); in dcn30_init_hw()
448 hws->funcs.disable_vga(dc->hwseq); in dcn30_init_hw()
514 if (hws->funcs.enable_power_gating_plane) in dcn30_init_hw()
[all …]
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