/openbsd/gnu/usr.bin/gcc/gcc/testsuite/gcc.c-torture/unsorted/ |
H A D | UHIcmp.c | 18 #define imm1 33 macro 35 {if (reg0 <= imm1) return 1; else return 0;} 67 {if (indreg0 <= imm1) return 1; else return 0;} 99 {if (imm0 <= imm1) return 1; else return 0;} 131 {if (limm0 <= imm1) return 1; else return 0;} 163 {if (adr0 <= imm1) return 1; else return 0;} 195 {if (adrreg0 <= imm1) return 1; else return 0;} 227 {if (adrx0 <= imm1) return 1; else return 0;} 259 {if (regx0 <= imm1) return 1; else return 0;}
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H A D | UQIcmp.c | 18 #define imm1 33 macro 35 {if (reg0 <= imm1) return 1; else return 0;} 67 {if (indreg0 <= imm1) return 1; else return 0;} 99 {if (imm0 <= imm1) return 1; else return 0;} 131 {if (limm0 <= imm1) return 1; else return 0;} 163 {if (adr0 <= imm1) return 1; else return 0;} 195 {if (adrreg0 <= imm1) return 1; else return 0;} 227 {if (adrx0 <= imm1) return 1; else return 0;} 259 {if (regx0 <= imm1) return 1; else return 0;}
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H A D | USIcmp.c | 18 #define imm1 33 macro 35 {if (reg0 <= imm1) return 1; else return 0;} 67 {if (indreg0 <= imm1) return 1; else return 0;} 99 {if (imm0 <= imm1) return 1; else return 0;} 131 {if (limm0 <= imm1) return 1; else return 0;} 163 {if (adr0 <= imm1) return 1; else return 0;} 195 {if (adrreg0 <= imm1) return 1; else return 0;} 227 {if (adrx0 <= imm1) return 1; else return 0;} 259 {if (regx0 <= imm1) return 1; else return 0;}
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H A D | DFcmp.c | 18 #define imm1 33 macro 35 {if (reg0 <= imm1) return 1; else return 0;} 67 {if (indreg0 <= imm1) return 1; else return 0;} 99 {if (imm0 <= imm1) return 1; else return 0;} 131 {if (limm0 <= imm1) return 1; else return 0;} 163 {if (adr0 <= imm1) return 1; else return 0;} 195 {if (adrreg0 <= imm1) return 1; else return 0;} 227 {if (adrx0 <= imm1) return 1; else return 0;} 259 {if (regx0 <= imm1) return 1; else return 0;}
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H A D | QIcmp.c | 18 #define imm1 33 macro 35 {if (reg0 <= imm1) return 1; else return 0;} 67 {if (indreg0 <= imm1) return 1; else return 0;} 99 {if (imm0 <= imm1) return 1; else return 0;} 131 {if (limm0 <= imm1) return 1; else return 0;} 163 {if (adr0 <= imm1) return 1; else return 0;} 195 {if (adrreg0 <= imm1) return 1; else return 0;} 227 {if (adrx0 <= imm1) return 1; else return 0;} 259 {if (regx0 <= imm1) return 1; else return 0;}
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H A D | SIcmp.c | 18 #define imm1 33 macro 35 {if (reg0 <= imm1) return 1; else return 0;} 67 {if (indreg0 <= imm1) return 1; else return 0;} 99 {if (imm0 <= imm1) return 1; else return 0;} 131 {if (limm0 <= imm1) return 1; else return 0;} 163 {if (adr0 <= imm1) return 1; else return 0;} 195 {if (adrreg0 <= imm1) return 1; else return 0;} 227 {if (adrx0 <= imm1) return 1; else return 0;} 259 {if (regx0 <= imm1) return 1; else return 0;}
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H A D | HIcmp.c | 18 #define imm1 33 macro 35 {if (reg0 <= imm1) return 1; else return 0;} 67 {if (indreg0 <= imm1) return 1; else return 0;} 99 {if (imm0 <= imm1) return 1; else return 0;} 131 {if (limm0 <= imm1) return 1; else return 0;} 163 {if (adr0 <= imm1) return 1; else return 0;} 195 {if (adrreg0 <= imm1) return 1; else return 0;} 227 {if (adrx0 <= imm1) return 1; else return 0;} 259 {if (regx0 <= imm1) return 1; else return 0;}
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H A D | SIset.c | 14 #define imm1 33 macro 35 {reg0 = imm1; } 67 {indreg0 = imm1; } 99 {adr0 = imm1; } 131 {adrreg0 = imm1; } 163 {adrx0 = imm1; } 195 {regx0 = imm1; }
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H A D | QIset.c | 14 #define imm1 33 macro 35 {reg0 = imm1; } 67 {indreg0 = imm1; } 99 {adr0 = imm1; } 131 {adrreg0 = imm1; } 163 {adrx0 = imm1; } 195 {regx0 = imm1; }
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H A D | SFset.c | 14 #define imm1 33 macro 35 {reg0 = imm1; } 67 {indreg0 = imm1; } 99 {adr0 = imm1; } 131 {adrreg0 = imm1; } 163 {adrx0 = imm1; } 195 {regx0 = imm1; }
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H A D | HIset.c | 14 #define imm1 33 macro 35 {reg0 = imm1; } 67 {indreg0 = imm1; } 99 {adr0 = imm1; } 131 {adrreg0 = imm1; } 163 {adrx0 = imm1; } 195 {regx0 = imm1; }
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H A D | gen_tst.c | 18 #define imm1 33 macro
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/openbsd/gnu/llvm/llvm/lib/Target/Xtensa/ |
H A D | XtensaInstrInfo.td | 139 def EXTUI : RRR_Inst<0x00, 0x04, 0x00, (outs AR:$r), (ins AR:$t, uimm5:$imm1, imm1_16:$imm2), 140 "extui\t$r, $t, $imm1, $imm2", []> { 141 bits<5> imm1; 144 let s = imm1{3-0}; 145 let Inst{16} = imm1{4};
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/openbsd/gnu/usr.bin/binutils-2.17/cpu/ |
H A D | m32r.cpu | 671 (dnop imm1 "1 bit immediate" ((MACH m32rx,m32r2) HASH-PREFIX) h-uint f-imm1) 1894 "rac $accd,$accs,$imm1" 1895 (+ OP1_5 accd (f-bits67 0) OP2_9 accs (f-bit14 0) imm1) 1897 (set tmp1 (sll accs imm1)) 1914 (emit rac-dsi accd (f-accs 0) (f-imm1 0)) 1920 (emit rac-dsi accd accs (f-imm1 0)) 1953 "rach $accd,$accs,$imm1" 1954 (+ OP1_5 accd (f-bits67 0) OP2_8 accs (f-bit14 0) imm1) 1956 (set tmp1 (sll accs imm1)) 1973 (emit rach-dsi accd (f-accs 0) (f-imm1 0)) [all …]
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H A D | m32c.cpu | 2022 h-sint DFLT f-imm1-S 6524 ;<arith>.L:S #imm1,An -- for m32c 6527 (define-pmacro (binary-arith32-l-s-imm1-an op opc1 opc2 sem) 6529 (dni (.sym op 32.l-s-imm1-S-an) 6530 (.str op ".l 32-imm1-S-an") 7061 ;<insn>.size #imm1,#imm2,dst -- for m32c 7615 (define-pmacro (clip-sem mode imm1 imm2 dest) 7617 (if (gt mode imm1 dest) 7618 (set dest imm1)) 7623 (insn-imm1-imm2-dst-Prefixed clip #x8 #x3 #xE clip-sem) [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/AArch64/ |
H A D | AArch64SMEInstrInfo.td | 140 // MSR SVCRSM, #<imm1> 141 // MSR SVCRZA, #<imm1> 142 // MSR SVCRSMZA, #<imm1>
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/openbsd/gnu/gcc/gcc/config/sparc/ |
H A D | sparc.c | 2886 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL; in legitimate_address_p() local 2920 imm1 = rs2; in legitimate_address_p() 2951 imm1 = XEXP (rs1, 1); in legitimate_address_p() 2953 if (! CONSTANT_P (imm1) || SPARC_SYMBOL_REF_TLS_P (rs1)) in legitimate_address_p() 2960 imm1 = XEXP (addr, 1); in legitimate_address_p() 2962 if (! CONSTANT_P (imm1) || SPARC_SYMBOL_REF_TLS_P (rs1)) in legitimate_address_p()
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/openbsd/gnu/llvm/llvm/lib/Target/RISCV/ |
H A D | RISCVInstrInfo.td | 420 // Check if (add r, imm) can be optimized to (ADDI (ADDI r, imm0), imm1), 421 // in which imm = imm0 + imm1 and both imm0 and imm1 are simm12. We make imm0 422 // as large as possible and imm1 as small as possible so that we might be able
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/openbsd/gnu/llvm/llvm/lib/Target/X86/ |
H A D | README-SSE.txt | 467 INSERTPS can match any insert (extract, imm1), imm2 for 4 x float, and insert
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/openbsd/gnu/llvm/llvm/lib/Target/Mips/ |
H A D | MipsFastISel.cpp | 232 unsigned Op0, uint64_t imm1, uint64_t imm2, in fastEmitInst_riir() argument
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/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrP10.td | 436 // PO T XO TX imm1 ]. 461 // PO T XO IX TX imm1 ].
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/openbsd/gnu/llvm/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrFormats.td | 3179 ImmOpWithPattern imm1, ImmOpWithPattern imm2> 3180 : InstIE<opcode, (outs), (ins imm1:$I1, imm2:$I2),
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/openbsd/gnu/llvm/llvm/lib/Target/ARM/ |
H A D | ARMInstrThumb2.td | 4708 // SETPAN #imm1
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H A D | ARMInstrInfo.td | 4867 // SETPAN #imm1
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/openbsd/gnu/llvm/llvm/lib/Target/NVPTX/ |
H A D | NVPTXIntrinsics.td | 1484 def imm1 : NVPTXInst<(outs regclass:$dst),
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