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Searched refs:inst_idx (Results 1 – 12 of 12) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dvcn_v4_0.c472 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), in vcn_v4_0_mc_resume_dpg_mode()
526 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0), in vcn_v4_0_mc_resume_dpg_mode()
776 int inst_idx, uint8_t indirect) in vcn_v4_0_disable_clock_gating_dpg_mode() argument
895 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v4_0_enable_ras()
900 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v4_0_enable_ras()
930 …adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_ad… in vcn_v4_0_start_dpg_mode()
958 VCN, inst_idx, regUVD_MPC_CNTL), in vcn_v4_0_start_dpg_mode()
962 VCN, inst_idx, regUVD_MPC_SET_MUXA0), in vcn_v4_0_start_dpg_mode()
969 VCN, inst_idx, regUVD_MPC_SET_MUXB0), in vcn_v4_0_start_dpg_mode()
976 VCN, inst_idx, regUVD_MPC_SET_MUX), in vcn_v4_0_start_dpg_mode()
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H A Dvcn_v3_0.c75 int inst_idx, struct dpg_pause_state *new_state);
532 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v3_0_mc_resume_dpg_mode()
586 VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), in vcn_v3_0_mc_resume_dpg_mode()
958 …adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_ad… in vcn_v3_0_start_dpg_mode()
987 VCN, inst_idx, mmUVD_MPC_CNTL), in vcn_v3_0_start_dpg_mode()
991 VCN, inst_idx, mmUVD_MPC_SET_MUXA0), in vcn_v3_0_start_dpg_mode()
998 VCN, inst_idx, mmUVD_MPC_SET_MUXB0), in vcn_v3_0_start_dpg_mode()
1005 VCN, inst_idx, mmUVD_MPC_SET_MUX), in vcn_v3_0_start_dpg_mode()
1032 VCN, inst_idx, mmUVD_MASTINT_EN), in vcn_v3_0_start_dpg_mode()
1042 ring = &adev->vcn.inst[inst_idx].ring_dec; in vcn_v3_0_start_dpg_mode()
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H A Dvcn_v2_5.c64 int inst_idx, struct dpg_pause_state *new_state);
804 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v2_6_enable_ras()
809 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v2_6_enable_ras()
814 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v2_6_enable_ras()
835 …adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_ad… in vcn_v2_5_start_dpg_mode()
898 vcn_v2_6_enable_ras(adev, inst_idx, indirect); in vcn_v2_5_start_dpg_mode()
915 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); in vcn_v2_5_start_dpg_mode()
917 ring = &adev->vcn.inst[inst_idx].ring_dec; in vcn_v2_5_start_dpg_mode()
949 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); in vcn_v2_5_start_dpg_mode()
952 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, in vcn_v2_5_start_dpg_mode()
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H A Dvcn_v4_0_3.c58 int inst_idx, bool indirect);
352 vcn_inst = GET_INST(VCN, inst_idx); in vcn_v4_0_3_mc_resume()
540 vcn_inst = GET_INST(VCN, inst_idx); in vcn_v4_0_3_disable_clock_gating()
628 int inst_idx, uint8_t indirect) in vcn_v4_0_3_disable_clock_gating_dpg_mode() argument
684 vcn_inst = GET_INST(VCN, inst_idx); in vcn_v4_0_3_enable_clock_gating()
736 vcn_inst = GET_INST(VCN, inst_idx); in vcn_v4_0_3_start_dpg_mode()
748 inst_idx, adev->vcn.inst[inst_idx].aid_id); in vcn_v4_0_3_start_dpg_mode()
1238 vcn_inst = GET_INST(VCN, inst_idx); in vcn_v4_0_3_stop_dpg_mode()
1762 int inst_idx, bool indirect) in vcn_v4_0_3_enable_ras() argument
1773 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v4_0_3_enable_ras()
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H A Damdgpu_vcn.h82 ({ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
83 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
88 RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA); \
93 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA, value); \
94 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
95 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
102 #define SOC15_DPG_MODE_OFFSET(ip, inst_idx, reg) \ argument
137 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \
141 RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA); \
150 VCN, GET_INST(VCN, inst_idx), \
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H A Dvcn_v1_0.c54 int inst_idx, struct dpg_pause_state *new_state);
1218 int inst_idx, struct dpg_pause_state *new_state) in vcn_v1_0_pause_dpg_mode() argument
1226 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { in vcn_v1_0_pause_dpg_mode()
1228 adev->vcn.inst[inst_idx].pause_state.fw_based, in vcn_v1_0_pause_dpg_mode()
1229 adev->vcn.inst[inst_idx].pause_state.jpeg, in vcn_v1_0_pause_dpg_mode()
1278 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; in vcn_v1_0_pause_dpg_mode()
1282 if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) { in vcn_v1_0_pause_dpg_mode()
1284 adev->vcn.inst[inst_idx].pause_state.fw_based, in vcn_v1_0_pause_dpg_mode()
1285 adev->vcn.inst[inst_idx].pause_state.jpeg, in vcn_v1_0_pause_dpg_mode()
1339 adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg; in vcn_v1_0_pause_dpg_mode()
H A Daqua_vanjaram.c70 uint32_t inst_idx, struct amdgpu_ring *ring) in aqua_vanjaram_set_xcp_id() argument
80 inst_mask = 1 << inst_idx; in aqua_vanjaram_set_xcp_id()
95 inst_mask = 1 << (inst_idx * 2); in aqua_vanjaram_set_xcp_id()
H A Damdgpu_vcn.c1250 int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx, in amdgpu_vcn_psp_update_sram() argument
1255 (inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : in amdgpu_vcn_psp_update_sram()
1257 .mc_addr = adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, in amdgpu_vcn_psp_update_sram()
1258 .ucode_size = ((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - in amdgpu_vcn_psp_update_sram()
1259 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr), in amdgpu_vcn_psp_update_sram()
H A Djpeg_v4_0_3.c414 static void jpeg_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx) in jpeg_v4_0_3_disable_clock_gating() argument
419 jpeg_inst = GET_INST(JPEG, inst_idx); in jpeg_v4_0_3_disable_clock_gating()
439 static void jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx) in jpeg_v4_0_3_enable_clock_gating() argument
444 jpeg_inst = GET_INST(JPEG, inst_idx); in jpeg_v4_0_3_enable_clock_gating()
H A Dvcn_v2_0.c62 int inst_idx, struct dpg_pause_state *new_state);
1202 int inst_idx, struct dpg_pause_state *new_state) in vcn_v2_0_pause_dpg_mode() argument
1209 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { in vcn_v2_0_pause_dpg_mode()
1211 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); in vcn_v2_0_pause_dpg_mode()
1272 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; in vcn_v2_0_pause_dpg_mode()
/openbsd/gnu/llvm/lldb/examples/python/
H A Dsymbolication.py580 for inst_idx, inst in enumerate(instructions):
583 pc_index = inst_idx
606 end_idx = inst_idx
609 if end_idx > inst_idx:
610 end_idx = inst_idx
/openbsd/gnu/llvm/lldb/source/Core/
H A DIOHandlerCursesGUI.cpp7132 const uint32_t inst_idx = m_first_visible_line + i; in WindowDelegateDraw() local
7133 Instruction *inst = insts.GetInstructionAtIndex(inst_idx).get(); in WindowDelegateDraw()
7139 const bool is_pc_line = frame_sp && inst_idx == pc_idx; in WindowDelegateDraw()
7140 const bool line_is_selected = m_selected_line == inst_idx; in WindowDelegateDraw()