Searched refs:isBeforeLegalize (Results 1 – 10 of 10) sorted by relevance
/openbsd/gnu/llvm/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 1599 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformDAGCombine() 1615 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformDAGCombine() 1775 if (!DCI.isBeforeLegalize() || in PerformDAGCombine()
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/openbsd/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
H A D | TargetLowering.cpp | 601 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedBits() 617 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedBits() 2752 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedVectorElts() 4016 !DCI.isBeforeLegalize()); in foldSetCCWithBinOp() 4303 DCI.isBeforeLegalize() && N0->hasOneUse()) { in SimplifySetCC() 4390 if (DCI.isBeforeLegalize() && in SimplifySetCC() 4842 getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize()); in SimplifySetCC() 4868 EVT ShiftTy = getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize()); in SimplifySetCC() 6251 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout(), !DCI.isBeforeLegalize()); in prepareUREMEqFold() 6500 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout(), !DCI.isBeforeLegalize()); in prepareSREMEqFold()
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/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 2981 if (!DCI.isBeforeLegalize()) in performLoadCombine() 3034 if (!DCI.isBeforeLegalize()) in performStoreCombine() 4252 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformDAGCombine()
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H A D | SIISelLowering.cpp | 9652 if (DCI.isBeforeLegalize()) in performAndCombine() 10814 if (Vec.hasOneUse() && DCI.isBeforeLegalize() && VecEltVT == ResVT) { in performExtractVectorEltCombine() 10863 if (!DCI.isBeforeLegalize()) in performExtractVectorEltCombine() 11694 if (!DCI.isBeforeLegalize()) { in PerformDAGCombine()
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/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/ |
H A D | TargetLowering.h | 3939 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; } in isBeforeLegalize() function
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/openbsd/gnu/llvm/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 12562 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON() in AddCombineBUILD_VECTORToVPADDL() 13382 if (DCI.isBeforeLegalize()) return SDValue(); in PerformADDECombine() 13761 if (DCI.isBeforeLegalize()) in PerformSHLSimplify() 14069 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformMULCombine() 14147 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in CombineANDShift() 16116 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformVLDCombine() 16124 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformMVEVLDCombine() 17495 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformShiftCombine()
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/openbsd/gnu/llvm/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 16486 if (!Subtarget->hasSVE() || DCI.isBeforeLegalize()) in performFirstTrueTestVectorCombine() 16516 if (!Subtarget->hasSVE() || DCI.isBeforeLegalize()) in performLastTrueTestVectorCombine() 17827 if (DCI.isBeforeLegalize()) in tryConvertSVEWideCompare() 19204 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in performTBISimplification() 19530 if (!DCI.isBeforeLegalize()) in performMaskedGatherScatterCombine() 19566 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in performNEONPostLDSTCombine() 20284 if (DCI.isBeforeLegalize() && VT.isScalarInteger() && in performSETCCCombine() 20668 assert(DCI.isBeforeLegalize() || in performSelectCombine()
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/openbsd/gnu/llvm/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 43819 if (DCI.isBeforeLegalize()) { in combineBitcast() 45631 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in combineVSelectToBLENDV() 46197 if (DCI.isBeforeLegalize() && !Subtarget.hasAVX512() && in combineSelect() 47099 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) { in combineCMov() 47586 if (DCI.isBeforeLegalize() && VT.isVector()) in combineMul() 47598 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in combineMul() 50332 RegVT.getScalarType() == MVT::i1 && DCI.isBeforeLegalize()) { in combineLoad() 50850 if (DCI.isBeforeLegalize() || TLI.isTypeLegal(St->getMemoryVT())) in combineStore() 53476 isNullConstant(RHS) && !DCI.isBeforeLegalize()) { in combineSetCC() 53723 if (DCI.isBeforeLegalize()) { in combineGatherScatter() [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 14539 if (Subtarget.hasP9Altivec() && !DCI.isBeforeLegalize()) { in DAGCombineBuildVector() 15378 if (Subtarget.isPPC64() && !DCI.isBeforeLegalize() && in PerformDAGCombine() 15809 if (!DCI.isBeforeLegalize() || !Is64BitBswapOn64BitTgt || in PerformDAGCombine()
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/openbsd/gnu/llvm/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 10380 if (!DCI.isBeforeLegalize()) in PerformDAGCombine()
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