Searched refs:isSGPRClass (Results 1 – 14 of 14) sorted by relevance
186 static bool isSGPRClass(const TargetRegisterClass *RC) { in isSGPRClass() function192 return isSGPRClass(getRegClass(RCID)); in isSGPRClassID()290 return !isSGPRClass(RC); in isDivergentRegClass()
205 return SrcRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(DstRC) && in isVGPRToSGPRCopy()212 return DstRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(SrcRC) && in isSGPRToVGPRCopy()264 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg))) in foldVGPRCopyIntoRegSequence()308 assert(TRI->isSGPRClass(SrcRC) && in foldVGPRCopyIntoRegSequence()651 if (TRI->isSGPRClass(TII->getOpRegClass(MI, 0))) { in runOnMachineFunction()
953 if (RI.isSGPRClass(RC)) { in copyPhysReg()954 if (!RI.isSGPRClass(SrcRC)) { in copyPhysReg()978 (SrcRC == RC || RI.isSGPRClass(SrcRC)))) { in copyPhysReg()1104 if (RI.isSGPRClass(RegClass)) { in materializeImmediate()1595 if (RI.isSGPRClass(RC)) { in storeRegToStackSlot()1796 if (RI.isSGPRClass(RC)) { in loadRegFromStackSlot()2883 return RI.isSGPRClass(RC); in canInsertSelect()4978 else if (RI.isSGPRClass(RC)) in legalizeOpWithMove()5879 if (VRC || !RI.isSGPRClass(getOpRegClass(MI, 0))) { in legalizeOperands()7429 bool IsRequiredSGPR = RI.isSGPRClass(OpRC); in findUsedSGPR()[all …]
232 if ((RC->MC->getSizeInBits() != 64 || !TRI->isSGPRClass(RC)) && in runOnMachineFunction()
43 return STI->isSGPRClass(RC) in getRegKind()
82 return static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(&RC); in onlyAllocateSGPRs()87 return !static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(&RC); in onlyAllocateVGPRs()
853 if (!RC || !TRI->isSGPRClass(RC)) in isInlineAsmSourceOfDivergence()
1213 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegBaseClass(MO.getReg()))) { in fixSMEMtoVectorWriteHazards()1294 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegBaseClass(MO.getReg()))) in fixVcmpxExecWARHazard()
1435 return RC && TRI.isSGPRClass(RC); in IsCopyFromSGPR()2933 if (!RC || SIRI->isSGPRClass(RC)) in isVGPRImm()
2361 bool IsSALU = isSGPRClass(TII->getOpRegClass(*MI, FIOperandNum)); in eliminateFrameIndex()2786 return RC ? isSGPRClass(RC) : false; in isSGPRReg()
659 if (TRI->isSGPRClass(SrcRC) && TRI->hasVectorRegisters(DestRC)) { in foldOperand()
3836 if (TII->getRegisterInfo().isSGPRClass(IdxRC)) { in emitIndirectSrc()3940 if (TII->getRegisterInfo().isSGPRClass(IdxRC)) { in emitIndirectDst()12325 else if (SIRegisterInfo::isSGPRClass(RC)) in getRegForInlineAsmConstraint()13045 if (!TRI->isSGPRClass(RC) && !isDivergent) in getRegClassFor()13047 else if (TRI->isSGPRClass(RC) && isDivergent) in getRegClassFor()13122 if (RC && SIRI->isSGPRClass(RC)) in requiresUniformRegister()
282 if (TRI->isSGPRClass(&RC)) { in getRegBankFromRegClass()
162 TRI.isSGPRClass(SrcRC) ? AMDGPU::S_AND_B32 : AMDGPU::V_AND_B32_e32; in selectCOPY()