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Searched refs:isVerilogBegin (Results 1 – 3 of 3) sorted by relevance

/openbsd/gnu/llvm/clang/lib/Format/
H A DUnwrappedLineParser.cpp881 (Keywords.isVerilogBegin(*FormatTok) || VerilogHierarchy))) && in parseBlock()
2019 if (Keywords.isVerilogBegin(*FormatTok) || in parseStructuralElement()
2759 return Style.isVerilog() ? Keywords.isVerilogBegin(Tok) in isBlockBegin()
4327 else if (!Style.IndentCaseBlocks && Keywords.isVerilogBegin(*FormatTok)) in parseVerilogCaseLabel()
H A DFormatToken.h1752 bool isVerilogBegin(const FormatToken &Tok) const { in isVerilogBegin() function
H A DTokenAnnotator.cpp980 Keywords.isVerilogBegin(*Tok->Previous)) { in consumeToken()
4452 if (!Keywords.isVerilogBegin(Right) && Keywords.isVerilogEndOfLabel(Left)) in mustBreakBefore()