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Searched refs:ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE (Results 1 – 14 of 14) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h7796 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … macro
H A Ddcn_3_0_1_offset.h12639 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … macro
H A Ddcn_1_0_offset.h13483 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … macro
H A Ddcn_2_1_0_offset.h13243 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … macro
H A Ddcn_3_1_4_offset.h554 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … macro
H A Ddcn_3_1_5_offset.h14559 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … macro
H A Ddcn_3_2_0_offset.h13950 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … macro
H A Ddcn_3_2_1_offset.h13929 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … macro
H A Ddcn_3_1_2_offset.h14453 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … macro
H A Ddcn_3_1_6_offset.h15050 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … macro
H A Ddcn_3_0_2_offset.h15532 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … macro
H A Ddcn_2_0_0_offset.h16907 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … macro
H A Ddcn_3_0_0_offset.h17255 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h17296 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … macro