Home
last modified time | relevance | path

Searched refs:mmCP_MES_IC_BASE_CNTL (Results 1 – 3 of 3) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dmes_v10_1.c532 WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_CNTL, 0); in mes_v10_1_load_microcode()
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h10293 #define mmCP_MES_IC_BASE_CNTL … macro
H A Dgc_10_3_0_offset.h10015 #define mmCP_MES_IC_BASE_CNTL … macro