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Searched refs:mmRLC_RLCS_POWER_BRAKE_CNTL_TH1 (Results 1 – 2 of 2) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h9865 #define mmRLC_RLCS_POWER_BRAKE_CNTL_TH1 … macro
H A Dgc_10_3_0_offset.h9773 #define mmRLC_RLCS_POWER_BRAKE_CNTL_TH1 … macro