| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn32/ |
| H A D | dcn32_resource_helpers.c | 128 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_merge_pipes_for_subvp()
173 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_all_pipes_have_stream_and_plane()
190 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_in_use()
215 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_any_surfaces_rotated()
309 for (j = 0; j < dc->res_pool->pipe_count; j++) { in dcn32_determine_det_override()
320 for (k = 0; k < dc->res_pool->pipe_count; k++) { in dcn32_determine_det_override()
346 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn32_determine_det_override()
413 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_save_mall_state()
441 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_restore_mall_state()
646 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_drr_admissable()
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| H A D | dcn32_hwseq.c | 228 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_calculate_cab_allocation()
347 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_commit_subvp_config()
378 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_pipe_control_lock()
398 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_pipe_control_lock()
608 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_update_force_pstate()
629 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_update_force_pstate()
660 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_update_mall_sel()
720 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_program_mall_pipe_config()
933 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_init_hw()
1207 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_resync_fifo_dccg_dio()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_resource.c | 1109 for (i = 0; i < pool->base.pipe_count; i++) { in dcn20_resource_destruct()
1870 if (plane_count > dc->res_pool->pipe_count / 2) in dcn20_validate_apply_pipe_split_flags()
2233 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_dwbc_create() local
2235 for (i = 0; i < pipe_count; i++) { in dcn20_dwbc_create()
2256 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_mmhubbub_create() local
2258 ASSERT(pipe_count > 0); in dcn20_mmhubbub_create()
2260 for (i = 0; i < pipe_count; i++) { in dcn20_mmhubbub_create()
2406 pool->base.pipe_count = 5; in dcn20_resource_construct()
2410 pool->base.pipe_count = 6; in dcn20_resource_construct()
2609 for (i = 0; i < pool->base.pipe_count; i++) { in dcn20_resource_construct()
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| H A D | dcn20_hwseq.c | 1810 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
1831 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
1846 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
1853 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
1873 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
1882 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
1904 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
1969 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_post_unlock_program_front_end()
1979 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_post_unlock_program_front_end()
2556 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_reset_back_end_for_pipe()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/core/ |
| H A D | amdgpu_dc.c | 1113 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_dangling_plane()
1210 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_vbios_mode_if_required()
1308 full_pipe_count = dc->res_pool->pipe_count; in dc_create()
1401 int pipe_count = dc->res_pool->pipe_count; in enable_timing_multisync() local
1404 for (i = 0; i < pipe_count; i++) { in enable_timing_multisync()
1427 int pipe_count = dc->res_pool->pipe_count; in program_timing_sync() local
1430 for (i = 0; i < pipe_count; i++) { in program_timing_sync()
1439 for (i = 0; i < pipe_count; i++) { in program_timing_sync()
1453 for (j = i + 1; j < pipe_count; j++) { in program_timing_sync()
2197 for (i = 0; i < dc->res_pool->pipe_count; i++) in dc_post_update_surfaces_to_stream()
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| H A D | dc_surface.c | 150 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
163 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_hw_sequencer_debug.c | 134 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_hubp_states()
204 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_rq_states()
249 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_dlg_states()
303 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_ttu_states()
342 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_cm_states()
395 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_mpcc_states()
510 for (i = 0; i < pool->pipe_count; i++) { in dcn10_clear_hubp_underflow()
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| H A D | dcn10_hw_sequencer.c | 102 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
176 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
208 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
233 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
265 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
298 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hw_state()
340 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hw_state()
1061 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn10_reset_back_end_for_pipe()
1065 if (i == dc->res_pool->pipe_count) in dcn10_reset_back_end_for_pipe()
3259 for (i = 0; i < res_pool->pipe_count; i++) { in get_hubp_by_inst()
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| H A D | dcn10_resource.c | 926 for (i = 0; i < pool->base.pipe_count; i++) { in dcn10_resource_destruct()
1338 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn10_resource_construct()
1341 pool->base.pipe_count = 3; in dcn10_resource_construct()
1556 for (i = 0; i < pool->base.pipe_count; i++) { in dcn10_resource_construct()
1625 pool->base.pipe_count = j; in dcn10_resource_construct()
1631 dc->dml.ip.max_num_dpp = pool->base.pipe_count; in dcn10_resource_construct()
1632 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; in dcn10_resource_construct()
1653 dc->caps.max_planes = pool->base.pipe_count; in dcn10_resource_construct()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dce60/ |
| H A D | dce60_resource.c | 801 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_resource_destruct()
874 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_validate_bandwidth()
960 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
1035 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_construct()
1097 dc->caps.max_planes = pool->base.pipe_count; in dce60_construct()
1155 pool->base.pipe_count = res_cap_61.num_timing_generator; in dce61_construct()
1233 for (i = 0; i < pool->base.pipe_count; i++) { in dce61_construct()
1295 dc->caps.max_planes = pool->base.pipe_count; in dce61_construct()
1353 pool->base.pipe_count = res_cap_64.num_timing_generator; in dce64_construct()
1427 for (i = 0; i < pool->base.pipe_count; i++) { in dce64_construct()
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| H A D | dce60_hw_sequencer.c | 70 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_should_enable_fbc()
86 if (i == dc->res_pool->pipe_count) in dce60_should_enable_fbc()
395 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_apply_ctx_for_surface()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dce80/ |
| H A D | dce80_resource.c | 808 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_resource_destruct()
881 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce80_validate_bandwidth()
967 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
1049 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_construct()
1111 dc->caps.max_planes = pool->base.pipe_count; in dce80_construct()
1169 pool->base.pipe_count = res_cap_81.num_timing_generator; in dce81_construct()
1249 for (i = 0; i < pool->base.pipe_count; i++) { in dce81_construct()
1311 dc->caps.max_planes = pool->base.pipe_count; in dce81_construct()
1369 pool->base.pipe_count = res_cap_83.num_timing_generator; in dce83_construct()
1446 for (i = 0; i < pool->base.pipe_count; i++) { in dce83_construct()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_resource.c | 1095 for (i = 0; i < pool->base.pipe_count; i++) { in dcn30_resource_destruct()
1176 for (i = 0; i < pool->base.pipe_count; i++) { in dcn30_resource_destruct()
1216 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_dwbc_create() local
1218 for (i = 0; i < pipe_count; i++) { in dcn30_dwbc_create()
1241 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_mmhubbub_create() local
1243 for (i = 0; i < pipe_count; i++) { in dcn30_mmhubbub_create()
1384 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_set_mcif_arb_params()
1511 loaded_ip->max_num_dpp = pool->base.pipe_count; in init_soc_bounding_box()
1720 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_internal_validate_bw()
2448 for (i = 0; i < pool->base.pipe_count; i++) { in dcn30_resource_construct()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn302/ |
| H A D | dcn302_resource.c | 708 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_dwbc_create() local
710 for (i = 0; i < pipe_count; i++) { in dcn302_dwbc_create()
743 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_mmhubbub_create() local
745 for (i = 0; i < pipe_count; i++) { in dcn302_mmhubbub_create()
963 loaded_ip->max_num_otg = pool->pipe_count; in init_soc_bounding_box()
964 loaded_ip->max_num_dpp = pool->pipe_count; in init_soc_bounding_box()
1019 for (i = 0; i < pool->pipe_count; i++) { in dcn302_resource_destruct()
1094 for (i = 0; i < pool->pipe_count; i++) { in dcn302_resource_destruct()
1213 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn302_resource_construct()
1366 for (i = 0; i < pool->pipe_count; i++) { in dcn302_resource_construct()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn303/ |
| H A D | dcn303_resource.c | 651 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_dwbc_create() local
653 for (i = 0; i < pipe_count; i++) { in dcn303_dwbc_create()
686 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_mmhubbub_create() local
688 for (i = 0; i < pipe_count; i++) { in dcn303_mmhubbub_create()
890 loaded_ip->max_num_otg = pool->pipe_count; in init_soc_bounding_box()
891 loaded_ip->max_num_dpp = pool->pipe_count; in init_soc_bounding_box()
945 for (i = 0; i < pool->pipe_count; i++) { in dcn303_resource_destruct()
1020 for (i = 0; i < pool->pipe_count; i++) { in dcn303_resource_destruct()
1136 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn303_resource_construct()
1278 for (i = 0; i < pool->pipe_count; i++) { in dcn303_resource_construct()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dce110/ |
| H A D | dce110_resource.c | 816 for (i = 0; i < pool->base.pipe_count; i++) { in dce110_resource_destruct()
979 dc->res_pool->pipe_count, in dce110_validate_bandwidth()
1269 pool->opps[pool->pipe_count] = &dce110_oppv->base; in underlay_create()
1270 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; in underlay_create()
1271 pool->mis[pool->pipe_count] = &dce110_miv->base; in underlay_create()
1272 pool->transforms[pool->pipe_count] = &dce110_xfmv->base; in underlay_create()
1273 pool->pipe_count++; in underlay_create()
1367 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1368 pool->base.underlay_pipe_index = pool->base.pipe_count; in dce110_resource_construct()
1443 for (i = 0; i < pool->base.pipe_count; i++) { in dce110_resource_construct()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 635 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_get_num_free_pipes()
755 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_enough_pipes_for_subvp()
805 for (i = 0; i < dc->res_pool->pipe_count; i++) { in subvp_subvp_schedulable()
884 for (i = 0; i < dc->res_pool->pipe_count; i++) { in subvp_drr_schedulable()
899 for (i = 0; i < dc->res_pool->pipe_count; i++) { in subvp_drr_schedulable()
981 for (i = 0; i < dc->res_pool->pipe_count; i++) { in subvp_vblank_schedulable()
1049 for (i = 0; i < dc->res_pool->pipe_count; i++) { in subvp_subvp_admissable()
1306 for (i = 0; i < dc->res_pool->pipe_count; i++) { in is_dtbclk_required()
1491 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_calculate_dlg_params()
1735 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_internal_validate_bw()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn301/ |
| H A D | dcn301_resource.c | 1065 for (i = 0; i < pool->base.pipe_count; i++) { in dcn301_destruct()
1175 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_dwbc_create() local
1177 for (i = 0; i < pipe_count; i++) { in dcn301_dwbc_create()
1200 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_mmhubbub_create() local
1202 for (i = 0; i < pipe_count; i++) { in dcn301_mmhubbub_create()
1300 loaded_ip->max_num_dpp = pool->base.pipe_count; in init_soc_bounding_box()
1420 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn301_resource_construct()
1575 for (i = 0; i < pool->base.pipe_count; i++) { in dcn301_resource_construct()
1618 pool->base.pipe_count = j; in dcn301_resource_construct()
1692 dc->caps.max_planes = pool->base.pipe_count; in dcn301_resource_construct()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/ |
| H A D | dc_dmub_srv.c | 308 for (j = 0; j < dc->res_pool->pipe_count; j++) { in dc_dmub_srv_populate_fams_pipe_info()
315 fams_pipe_data->pipe_count = pipe_idx; in dc_dmub_srv_populate_fams_pipe_info()
339 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dc_dmub_srv_p_state_delegate()
357 for (i = 0, k = 0; context && i < dc->res_pool->pipe_count; i++) { in dc_dmub_srv_p_state_delegate()
530 for (i = 0; i < dc->res_pool->pipe_count; i++) { in populate_subvp_cmd_vblank_pipe_info()
685 for (j = 0; j < dc->res_pool->pipe_count; j++) { in populate_subvp_cmd_pipe_info()
730 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_dmub_setup_subvp_dmub_command()
743 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dc_dmub_setup_subvp_dmub_command()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 529 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
564 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn31_calculate_wm_and_dlg_fp()
568 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
596 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn31_update_bw_bounding_box()
668 dcn3_15_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn315_update_bw_bounding_box()
735 dcn3_16_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn316_update_bw_bounding_box()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn314/ |
| H A D | dcn314_fpu.c | 196 dcn3_14_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn314_update_bw_bounding_box_fpu()
321 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn314_populate_dml_pipes_from_context_fpu()
412 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn314_populate_dml_pipes_from_context_fpu()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn315/ |
| H A D | dcn315_resource.c | 1397 for (i = 0; i < pool->base.pipe_count; i++) { in dcn315_resource_destruct()
1512 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create() local
1514 for (i = 0; i < pipe_count; i++) { in dcn31_dwbc_create()
1537 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create() local
1539 for (i = 0; i < pipe_count; i++) { in dcn31_mmhubbub_create()
1639 for (i = 0; i < dc->res_pool->pipe_count; i++) { in allow_pixel_rate_crb()
1674 for (i = 0, pipe_cnt = 0, crb_pipes = 0; i < dc->res_pool->pipe_count; i++) { in dcn315_populate_dml_pipes_from_context()
1740 for (i = 0, pipe_cnt = 0, crb_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn315_populate_dml_pipes_from_context()
1856 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn315_resource_construct()
2000 for (i = 0; i < pool->base.pipe_count; i++) { in dcn315_resource_construct()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dce100/ |
| H A D | dce100_resource.c | 760 for (i = 0; i < pool->base.pipe_count; i++) { in dce100_resource_destruct()
847 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce100_validate_bandwidth()
1068 pool->base.pipe_count = res_cap.num_timing_generator; in dce100_resource_construct()
1080 for (i = 0; i < pool->base.pipe_count; i++) { in dce100_resource_construct()
1143 dc->caps.max_planes = pool->base.pipe_count; in dce100_resource_construct()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn316/ |
| H A D | dcn316_resource.c | 1395 for (i = 0; i < pool->base.pipe_count; i++) { in dcn316_resource_destruct()
1510 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create() local
1512 for (i = 0; i < pipe_count; i++) { in dcn31_dwbc_create()
1535 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create() local
1537 for (i = 0; i < pipe_count; i++) { in dcn31_mmhubbub_create()
1625 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn316_populate_dml_pipes_from_context()
1743 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn316_resource_construct()
1887 for (i = 0; i < pool->base.pipe_count; i++) { in dcn316_resource_construct()
2004 dc->caps.max_planes = pool->base.pipe_count; in dcn316_resource_construct()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn31/ |
| H A D | dcn31_resource.c | 1397 for (i = 0; i < pool->base.pipe_count; i++) { in dcn31_resource_destruct()
1515 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create() local
1517 for (i = 0; i < pipe_count; i++) { in dcn31_dwbc_create()
1540 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create() local
1542 for (i = 0; i < pipe_count; i++) { in dcn31_mmhubbub_create()
1654 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_populate_dml_pipes_from_context()
1764 …display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_par… in dcn31_validate_bandwidth()
1887 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn31_resource_construct()
2051 for (i = 0; i < pool->base.pipe_count; i++) { in dcn31_resource_construct()
2186 dc->caps.max_planes = pool->base.pipe_count; in dcn31_resource_construct()
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