Home
last modified time | relevance | path

Searched refs:regBIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_7_0_offset.h12979 #define regBIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX … macro
H A Dnbio_7_2_0_offset.h15453 #define regBIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX … macro