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Searched refs:regBIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_7_0_offset.h18565 #define regBIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX … macro
H A Dnbio_7_2_0_offset.h17083 #define regBIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX … macro