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Searched refs:regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT (Results 1 – 3 of 3) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_9_0_offset.h2231 #define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT … macro
H A Dnbio_7_7_0_offset.h7478 #define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT … macro
H A Dnbio_7_2_0_offset.h8288 #define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT … macro