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Searched refs:regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R (Results 1 – 6 of 6) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_4_offset.h4830 #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R … macro
H A Ddcn_3_1_5_offset.h3676 #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R … macro
H A Ddcn_3_2_0_offset.h3443 #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R … macro
H A Ddcn_3_2_1_offset.h3442 #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R … macro
H A Ddcn_3_1_2_offset.h3917 #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R … macro
H A Ddcn_3_1_6_offset.h4137 #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R … macro