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Searched refs:regCM0_CM_POST_CSC_C21_C22_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_4_offset.h4757 #define regCM0_CM_POST_CSC_C21_C22_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h3603 #define regCM0_CM_POST_CSC_C21_C22_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h3370 #define regCM0_CM_POST_CSC_C21_C22_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h3369 #define regCM0_CM_POST_CSC_C21_C22_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h3844 #define regCM0_CM_POST_CSC_C21_C22_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h4064 #define regCM0_CM_POST_CSC_C21_C22_BASE_IDX … macro