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Searched refs:regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B (Results 1 – 6 of 6) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_4_offset.h5518 #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B … macro
H A Ddcn_3_1_5_offset.h4364 #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B … macro
H A Ddcn_3_2_0_offset.h3825 #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B … macro
H A Ddcn_3_2_1_offset.h3824 #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B … macro
H A Ddcn_3_1_2_offset.h4605 #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B … macro
H A Ddcn_3_1_6_offset.h4825 #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B … macro