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Searched refs:regCP_CPC_IC_BASE_CNTL (Results 1 – 6 of 6) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dgfx_v11_0.c2135 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v11_0_config_mec_cache()
2139 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v11_0_config_mec_cache()
2405 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2409 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
3493 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3497 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
H A Dgfx_v9_4_3.c1418 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v9_4_3_xcc_cp_compute_load_microcode()
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h585 #define regCP_CPC_IC_BASE_CNTL … macro
H A Dgc_9_4_3_offset.h3046 #define regCP_CPC_IC_BASE_CNTL … macro
H A Dgc_11_0_0_offset.h9730 #define regCP_CPC_IC_BASE_CNTL … macro
H A Dgc_11_0_3_offset.h10290 #define regCP_CPC_IC_BASE_CNTL … macro