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Searched refs:regDC_GPU_TIMER_READ (Results 1 – 6 of 6) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_4_offset.h1950 #define regDC_GPU_TIMER_READ … macro
H A Ddcn_3_1_5_offset.h454 #define regDC_GPU_TIMER_READ … macro
H A Ddcn_3_2_0_offset.h274 #define regDC_GPU_TIMER_READ … macro
H A Ddcn_3_2_1_offset.h274 #define regDC_GPU_TIMER_READ … macro
H A Ddcn_3_1_2_offset.h685 #define regDC_GPU_TIMER_READ … macro
H A Ddcn_3_1_6_offset.h889 #define regDC_GPU_TIMER_READ … macro