Home
last modified time | relevance | path

Searched refs:regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_4_offset.h11607 #define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h12343 #define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h11702 #define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h11711 #define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h12478 #define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h13074 #define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX … macro