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Searched refs:regDWB_OGAM_RAMA_START_BASE_CNTL_G (Results 1 – 6 of 6) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_4_offset.h12228 #define regDWB_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_3_1_5_offset.h894 #define regDWB_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_3_2_0_offset.h802 #define regDWB_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_3_2_1_offset.h802 #define regDWB_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_3_1_2_offset.h1191 #define regDWB_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_3_1_6_offset.h1395 #define regDWB_OGAM_RAMA_START_BASE_CNTL_G … macro