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Searched refs:regGDS_VMID0_SIZE (Results 1 – 6 of 6) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c941 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); in gfx_v9_4_3_xcc_init_compute_vmid()
959 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); in gfx_v9_4_3_xcc_init_gds_vmid()
2158 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, in gfx_v9_4_3_ring_emit_gds_switch()
H A Dgfx_v11_0.c1662 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0); in gfx_v11_0_init_compute_vmid()
1680 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0); in gfx_v11_0_init_gds_vmid()
4628 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid, in gfx_v11_0_ring_emit_gds_switch()
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h1280 #define regGDS_VMID0_SIZE … macro
H A Dgc_9_4_3_offset.h3460 #define regGDS_VMID0_SIZE … macro
H A Dgc_11_0_0_offset.h4766 #define regGDS_VMID0_SIZE … macro
H A Dgc_11_0_3_offset.h4990 #define regGDS_VMID0_SIZE … macro