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Searched refs:regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B (Results 1 – 6 of 6) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_4_offset.h13354 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B … macro
H A Ddcn_3_1_5_offset.h6442 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B … macro
H A Ddcn_3_2_0_offset.h4969 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B … macro
H A Ddcn_3_2_1_offset.h4968 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B … macro
H A Ddcn_3_1_2_offset.h6683 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B … macro
H A Ddcn_3_1_6_offset.h6903 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B … macro