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Searched refs:regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G (Results 1 – 6 of 6) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_4_offset.h13916 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G … macro
H A Ddcn_3_1_5_offset.h7004 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G … macro
H A Ddcn_3_2_0_offset.h5531 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G … macro
H A Ddcn_3_2_1_offset.h5530 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G … macro
H A Ddcn_3_1_2_offset.h7245 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G … macro
H A Ddcn_3_1_6_offset.h7465 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G … macro