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Searched refs:regSDMA0_QUEUE3_RB_AQL_CNTL_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_offset.h505 #define regSDMA0_QUEUE3_RB_AQL_CNTL_BASE_IDX … macro
H A Dgc_11_0_3_offset.h511 #define regSDMA0_QUEUE3_RB_AQL_CNTL_BASE_IDX … macro