Home
last modified time | relevance | path

Searched refs:regSDMA1_UTCL1_WR_XNACK0 (Results 1 – 3 of 3) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/sdma/
H A Dsdma_4_4_0_offset.h1161 #define regSDMA1_UTCL1_WR_XNACK0 … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_offset.h972 #define regSDMA1_UTCL1_WR_XNACK0 … macro
H A Dgc_11_0_3_offset.h978 #define regSDMA1_UTCL1_WR_XNACK0 … macro