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Searched refs:regUVD_VCPU_CACHE_OFFSET2 (Results 1 – 5 of 5) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c379 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET2, 0); in vcn_v4_0_3_mc_resume()
486 VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
948 regUVD_VCPU_CACHE_OFFSET2), 0); in vcn_v4_0_3_start_sriov()
H A Dvcn_v4_0.c414 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0); in vcn_v4_0_mc_resume()
512 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
1321 regUVD_VCPU_CACHE_OFFSET2), in vcn_v4_0_start_sriov()
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h38 #define regUVD_VCPU_CACHE_OFFSET2 macro
H A Dvcn_4_0_0_offset.h386 #define regUVD_VCPU_CACHE_OFFSET2 macro
H A Dvcn_4_0_3_offset.h388 #define regUVD_VCPU_CACHE_OFFSET2 macro