| /openbsd/sys/dev/pci/drm/amd/amdgpu/ |
| H A D | amdgpu_ring.c | 94 ring->wptr_old = ring->wptr; in amdgpu_ring_alloc()
97 ring->funcs->begin_use(ring); in amdgpu_ring_alloc()
148 ring->funcs->insert_nop(ring, count); in amdgpu_ring_commit()
154 ring->funcs->end_use(ring); in amdgpu_ring_commit()
166 ring->wptr = ring->wptr_old; in amdgpu_ring_undo()
169 ring->funcs->end_use(ring); in amdgpu_ring_undo()
229 adev->rings[ring->idx] = ring; in amdgpu_ring_init()
336 ring->ring = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); in amdgpu_ring_init()
344 (void **)&ring->ring); in amdgpu_ring_init()
377 (!ring->is_mes_queue && !(ring->adev->rings[ring->idx]))) in amdgpu_ring_fini()
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| H A D | jpeg_v1_0.c | 44 ring->ring[(*ptr)++] = 0; in jpeg_v1_0_decode_ring_patch_wreg()
47 ring->ring[(*ptr)++] = reg_offset; in jpeg_v1_0_decode_ring_patch_wreg()
50 ring->ring[(*ptr)++] = val; in jpeg_v1_0_decode_ring_patch_wreg()
73 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE2); in jpeg_v1_0_decode_ring_set_patch_ring()
74 ring->ring[ptr++] = 0; in jpeg_v1_0_decode_ring_set_patch_ring()
96 ring->ring[ptr++] = 0x01400200; in jpeg_v1_0_decode_ring_set_patch_ring()
98 ring->ring[ptr++] = val; in jpeg_v1_0_decode_ring_set_patch_ring()
102 ring->ring[ptr++] = 0; in jpeg_v1_0_decode_ring_set_patch_ring()
105 ring->ring[ptr++] = reg_offset; in jpeg_v1_0_decode_ring_set_patch_ring()
108 ring->ring[ptr++] = mask; in jpeg_v1_0_decode_ring_set_patch_ring()
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| H A D | amdgpu_fence.c | 170 am_fence->ring = ring; in amdgpu_fence_emit()
196 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, in amdgpu_fence_emit()
492 ring->fence_drv.cpu_addr = ring->fence_cpu_addr; in amdgpu_fence_driver_start_ring()
493 ring->fence_drv.gpu_addr = ring->fence_gpu_addr; in amdgpu_fence_driver_start_ring()
507 ring->name, ring->fence_drv.gpu_addr); in amdgpu_fence_driver_start_ring()
540 ring); in amdgpu_fence_driver_init_ring()
621 if (!ring || !ring->fence_drv.initialized) in amdgpu_fence_driver_hw_fini()
653 if (!ring || !ring->fence_drv.initialized || !ring->fence_drv.irq_src) in amdgpu_fence_driver_isr_toggle()
671 if (!ring || !ring->fence_drv.initialized) in amdgpu_fence_driver_sw_fini()
710 if (!ring || !ring->fence_drv.initialized) in amdgpu_fence_driver_hw_init()
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| H A D | amdgpu_ib.c | 168 if (!ring->sched.ready && !ring->is_mes_queue) { in amdgpu_ib_schedule()
207 ring->funcs->emit_mem_sync(ring); in amdgpu_ib_schedule()
211 ring->funcs->emit_wave_limit(ring, true); in amdgpu_ib_schedule()
214 ring->funcs->insert_start(ring); in amdgpu_ib_schedule()
219 amdgpu_ring_undo(ring); in amdgpu_ib_schedule()
298 amdgpu_ring_undo(ring); in amdgpu_ib_schedule()
303 ring->funcs->insert_end(ring); in amdgpu_ib_schedule()
314 ring->funcs->emit_wave_limit(ring, false); in amdgpu_ib_schedule()
418 if (!ring->sched.ready || !ring->funcs->test_ib) in amdgpu_ib_ring_tests()
439 ring->name); in amdgpu_ib_ring_tests()
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| H A D | amdgpu_ring_mux.c | 67 amdgpu_ring_write_multiple(real_ring, (void *)&ring->ring[start], in amdgpu_ring_mux_copy_pkt_from_sw_ring()
69 amdgpu_ring_write_multiple(real_ring, (void *)&ring->ring[0], end); in amdgpu_ring_mux_copy_pkt_from_sw_ring()
72 amdgpu_ring_write_multiple(real_ring, (void *)&ring->ring[start], end - start); in amdgpu_ring_mux_copy_pkt_from_sw_ring()
152 mux->real_ring = ring; in amdgpu_ring_mux_init()
224 e->ring = ring; in amdgpu_ring_mux_add_sw_ring()
358 amdgpu_ring_mux_set_wptr(mux, ring, ring->wptr); in amdgpu_sw_ring_set_wptr_gfx()
387 ring = mux->ring_entry[i].ring; in amdgpu_mcbp_scan()
446 offset = ring->wptr & ring->buf_mask; in amdgpu_sw_ring_ib_mark_offset()
562 chunk->end = ring->wptr; in amdgpu_ring_mux_end_ib()
583 ring = e->ring; in amdgpu_mcbp_handle_trailing_fence_irq()
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| H A D | jpeg_v2_0.c | 70 struct amdgpu_ring *ring; in jpeg_v2_0_sw_init() local
88 ring->use_doorbell = true; in jpeg_v2_0_sw_init()
91 snprintf(ring->name, sizeof(ring->name), "jpeg_dec"); in jpeg_v2_0_sw_init()
411 if (ring->use_doorbell) in jpeg_v2_0_dec_ring_get_wptr()
429 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); in jpeg_v2_0_dec_ring_set_wptr()
430 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in jpeg_v2_0_dec_ring_set_wptr()
566 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); in jpeg_v2_0_dec_ring_emit_ib()
570 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); in jpeg_v2_0_dec_ring_emit_ib()
605 amdgpu_ring_write(ring, in jpeg_v2_0_dec_ring_emit_reg_wait()
618 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; in jpeg_v2_0_dec_ring_emit_vm_flush()
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| H A D | amdgpu_ring.h | 367 ring->ring[i++] = ring->funcs->nop; in amdgpu_ring_clear_ring()
375 ring->ring[ring->wptr++ & ring->buf_mask] = v; in amdgpu_ring_write()
376 ring->wptr &= ring->ptr_mask; in amdgpu_ring_write()
377 ring->count_dw--; in amdgpu_ring_write()
389 occupied = ring->wptr & ring->buf_mask; in amdgpu_ring_write_multiple()
390 dst = (void *)&ring->ring[occupied]; in amdgpu_ring_write_multiple()
402 dst = (void *)ring->ring; in amdgpu_ring_write_multiple()
406 ring->wptr += count_dw; in amdgpu_ring_write_multiple()
407 ring->wptr &= ring->ptr_mask; in amdgpu_ring_write_multiple()
412 (ring->is_mes_queue && ring->mes_ctx ? \
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| H A D | uvd_v7_0.c | 89 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) in uvd_v7_0_enc_ring_get_rptr()
123 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) in uvd_v7_0_enc_ring_get_wptr()
156 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); in uvd_v7_0_enc_ring_set_wptr()
157 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in uvd_v7_0_enc_ring_set_wptr()
161 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) in uvd_v7_0_enc_ring_set_wptr()
446 ring = &adev->uvd.inst[j].ring; in uvd_v7_0_sw_init()
448 snprintf(ring->name, sizeof(ring->name), "uvd_%d", ring->me); in uvd_v7_0_sw_init()
459 snprintf(ring->name, sizeof(ring->name), "uvd_enc_%d.%d", ring->me, i); in uvd_v7_0_sw_init()
538 ring = &adev->uvd.inst[j].ring; in uvd_v7_0_hw_init()
816 ring = &adev->uvd.inst[i].ring; in uvd_v7_0_sriov_start()
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| H A D | vcn_sw_ring.c | 33 amdgpu_ring_write(ring, addr); in vcn_dec_sw_ring_emit_fence()
35 amdgpu_ring_write(ring, seq); in vcn_dec_sw_ring_emit_fence()
49 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_IB); in vcn_dec_sw_ring_emit_ib()
50 amdgpu_ring_write(ring, vmid); in vcn_dec_sw_ring_emit_ib()
53 amdgpu_ring_write(ring, ib->length_dw); in vcn_dec_sw_ring_emit_ib()
60 amdgpu_ring_write(ring, reg << 2); in vcn_dec_sw_ring_emit_reg_wait()
61 amdgpu_ring_write(ring, mask); in vcn_dec_sw_ring_emit_reg_wait()
62 amdgpu_ring_write(ring, val); in vcn_dec_sw_ring_emit_reg_wait()
68 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; in vcn_dec_sw_ring_emit_vm_flush()
84 amdgpu_ring_write(ring, reg << 2); in vcn_dec_sw_ring_emit_wreg()
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| H A D | sdma_v6_0.c | 102 BUG_ON(ring->ring[offset] != 0x55aa55aa); in sdma_v6_0_ring_patch_cond_exec()
104 cur = (ring->wptr - 1) & ring->buf_mask; in sdma_v6_0_ring_patch_cond_exec()
106 ring->ring[offset] = cur - offset; in sdma_v6_0_ring_patch_cond_exec()
108 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; in sdma_v6_0_ring_patch_cond_exec()
180 ring->doorbell_index, ring->wptr << 2); in sdma_v6_0_ring_set_wptr()
184 ring->doorbell_index, ring->wptr << 2); in sdma_v6_0_ring_set_wptr()
204 ring->doorbell_index, ring->wptr << 2); in sdma_v6_0_ring_set_wptr()
231 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v6_0_ring_insert_nop()
479 ring = &adev->sdma.instance[i].ring; in sdma_v6_0_gfx_resume()
764 ring = &adev->sdma.instance[i].ring; in sdma_v6_0_check_soft_reset()
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| H A D | jpeg_v4_0_3.c | 334 (ring->pipe ? (ring->pipe - 0x15) : 0), in jpeg_v4_0_3_hw_init()
602 ring->pipe ? (0x40 * ring->pipe - 0xc80) : 0); in jpeg_v4_0_3_dec_ring_get_rptr()
622 ring->pipe ? (0x40 * ring->pipe - 0xc80) : 0); in jpeg_v4_0_3_dec_ring_get_wptr()
637 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in jpeg_v4_0_3_dec_ring_set_wptr()
638 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in jpeg_v4_0_3_dec_ring_set_wptr()
642 (ring->pipe ? (0x40 * ring->pipe - 0xc80) : in jpeg_v4_0_3_dec_ring_set_wptr()
723 if (ring->adev->jpeg.inst[ring->me].aid_id) { in jpeg_v4_0_3_dec_ring_emit_fence()
736 if (ring->adev->jpeg.inst[ring->me].aid_id) { in jpeg_v4_0_3_dec_ring_emit_fence()
792 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); in jpeg_v4_0_3_dec_ring_emit_ib()
796 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); in jpeg_v4_0_3_dec_ring_emit_ib()
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| H A D | uvd_v6_0.c | 158 lower_32_bits(ring->wptr)); in uvd_v6_0_enc_ring_set_wptr()
184 amdgpu_ring_commit(ring); in uvd_v6_0_enc_ring_test_ring()
380 struct amdgpu_ring *ring; in uvd_v6_0_sw_init() local
412 ring = &adev->uvd.inst->ring; in uvd_v6_0_sw_init()
413 snprintf(ring->name, sizeof(ring->name), "uvd"); in uvd_v6_0_sw_init()
426 snprintf(ring->name, sizeof(ring->name), "uvd_enc%d", i); in uvd_v6_0_sw_init()
467 struct amdgpu_ring *ring = &adev->uvd.inst->ring; in uvd_v6_0_hw_init() local
502 amdgpu_ring_write(ring, 3); in uvd_v6_0_hw_init()
504 amdgpu_ring_commit(ring); in uvd_v6_0_hw_init()
722 struct amdgpu_ring *ring = &adev->uvd.inst->ring; in uvd_v6_0_start() local
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| H A D | sdma_v5_2.c | 112 BUG_ON(ring->ring[offset] != 0x55aa55aa); in sdma_v5_2_ring_patch_cond_exec()
114 cur = (ring->wptr - 1) & ring->buf_mask; in sdma_v5_2_ring_patch_cond_exec()
116 ring->ring[offset] = cur - offset; in sdma_v5_2_ring_patch_cond_exec()
118 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; in sdma_v5_2_ring_patch_cond_exec()
189 ring->doorbell_index, ring->wptr << 2); in sdma_v5_2_ring_set_wptr()
190 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); in sdma_v5_2_ring_set_wptr()
195 ring->me, in sdma_v5_2_ring_set_wptr()
213 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v5_2_ring_insert_nop()
216 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v5_2_ring_insert_nop()
500 ring = &adev->sdma.instance[i].ring; in sdma_v5_2_gfx_resume()
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| H A D | sdma_v5_0.c | 272 BUG_ON(ring->ring[offset] != 0x55aa55aa); in sdma_v5_0_ring_patch_cond_exec()
274 cur = (ring->wptr - 1) & ring->buf_mask; in sdma_v5_0_ring_patch_cond_exec()
276 ring->ring[offset] = cur - offset; in sdma_v5_0_ring_patch_cond_exec()
278 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; in sdma_v5_0_ring_patch_cond_exec()
355 ring->doorbell_index, ring->wptr << 2); in sdma_v5_0_ring_set_wptr()
359 ring->doorbell_index, ring->wptr << 2); in sdma_v5_0_ring_set_wptr()
379 ring->doorbell_index, ring->wptr << 2); in sdma_v5_0_ring_set_wptr()
406 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v5_0_ring_insert_nop()
409 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v5_0_ring_insert_nop()
693 ring = &adev->sdma.instance[i].ring; in sdma_v5_0_gfx_resume()
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| /openbsd/usr.bin/telnet/ |
| H A D | ring.c | 83 ring->supply = ring->consume = ring->bottom = buffer; in ring_init()
85 ring->top = ring->bottom+ring->size; in ring_init()
97 ring->mark = ring_decrement(ring, ring->supply, 1); in ring_mark()
153 ring->consume = ring->supply = ring->bottom; in ring_consumed()
168 return ring_subtract(ring, ring->consume, ring->supply); in ring_empty_count()
181 return ring_subtract(ring, ring->top, ring->supply); in ring_empty_consecutive()
186 return ring_subtract(ring, ring->consume, ring->supply); in ring_empty_consecutive()
204 return ring_subtract(ring, ring->mark, ring->consume); in ring_full_count()
216 if ((ring->supply < ring->consume) || ring_full(ring)) { in ring_full_consecutive()
217 return ring_subtract(ring, ring->top, ring->consume); in ring_full_consecutive()
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| /openbsd/sys/dev/pci/drm/radeon/ |
| H A D | radeon_ring.c | 87 ring->ring_free_dw -= ring->wptr; in radeon_ring_free_size()
88 ring->ring_free_dw &= ring->ptr_mask; in radeon_ring_free_size()
128 ring->wptr_old = ring->wptr; in radeon_ring_alloc()
174 rdev->asic->ring[ring->idx]->hdp_flush(rdev, ring); in radeon_ring_commit()
177 radeon_ring_write(ring, ring->nop); in radeon_ring_commit()
214 ring->wptr = ring->wptr_old; in radeon_ring_undo()
329 (*data)[i] = ring->ring[ptr++]; in radeon_ring_backup()
410 (void **)&ring->ring); in radeon_ring_init()
445 ring->ring = NULL; in radeon_ring_fini()
492 ring->wptr, ring->wptr); in radeon_debugfs_ring_info_show()
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| H A D | evergreen_dma.c | 43 struct radeon_ring *ring = &rdev->ring[fence->ring]; in evergreen_dma_fence_ring_emit() local
49 radeon_ring_write(ring, fence->seq); in evergreen_dma_fence_ring_emit()
55 radeon_ring_write(ring, 1); in evergreen_dma_fence_ring_emit()
69 struct radeon_ring *ring = &rdev->ring[ib->ring]; in evergreen_dma_ring_ib_execute() local
72 u32 next_rptr = ring->wptr + 4; in evergreen_dma_ring_ib_execute()
77 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in evergreen_dma_ring_ib_execute()
78 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); in evergreen_dma_ring_ib_execute()
79 radeon_ring_write(ring, next_rptr); in evergreen_dma_ring_ib_execute()
85 while ((ring->wptr & 7) != 5) in evergreen_dma_ring_ib_execute()
115 struct radeon_ring *ring = &rdev->ring[ring_index]; in evergreen_copy_dma() local
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| H A D | radeon_fence.c | 147 (*fence)->ring = ring; in radeon_fence_emit()
296 else if (radeon_ring_is_lockup(rdev, ring, &rdev->ring[ring])) { in radeon_fence_check_lockup()
302 fence_drv->sync_seq[ring], ring); in radeon_fence_check_lockup()
358 unsigned ring = fence->ring; in radeon_fence_is_signaled() local
640 if (seq[ring] >= rdev->fence_drv[ring].sync_seq[ring]) { in radeon_fence_wait_next()
666 seq[ring] = rdev->fence_drv[ring].sync_seq[ring]; in radeon_fence_wait_empty()
730 emitted = rdev->fence_drv[ring].sync_seq[ring] in radeon_fence_count_emitted()
852 ring, rdev->fence_drv[ring].gpu_addr); in radeon_fence_driver_start_ring()
898 for (ring = 0; ring < RADEON_NUM_RINGS; ring++) { in radeon_fence_driver_init()
918 for (ring = 0; ring < RADEON_NUM_RINGS; ring++) { in radeon_fence_driver_fini()
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| H A D | r600_dma.c | 51 struct radeon_ring *ring) in r600_dma_get_rptr() argument
121 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in r600_dma_resume() local
166 ring->wptr = 0; in r600_dma_resume()
171 ring->ready = true; in r600_dma_resume()
175 ring->ready = false; in r600_dma_resume()
270 ring->idx, tmp); in r600_dma_ring_test()
289 struct radeon_ring *ring = &rdev->ring[fence->ring]; in r600_dma_fence_ring_emit() local
406 struct radeon_ring *ring = &rdev->ring[ib->ring]; in r600_dma_ring_ib_execute() local
414 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in r600_dma_ring_ib_execute()
415 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); in r600_dma_ring_ib_execute()
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| H A D | uvd_v1_0.c | 84 struct radeon_ring *ring = &rdev->ring[fence->ring]; in uvd_v1_0_fence_emit() local
159 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in uvd_v1_0_init() local
173 ring->ready = true; in uvd_v1_0_init()
176 ring->ready = false; in uvd_v1_0_init()
250 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in uvd_v1_0_fini() local
253 ring->ready = false; in uvd_v1_0_fini()
265 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in uvd_v1_0_start() local
431 ring->idx, r); in uvd_v1_0_ring_test()
446 ring->idx, i); in uvd_v1_0_ring_test()
449 ring->idx, tmp); in uvd_v1_0_ring_test()
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| H A D | cik_sdma.c | 135 struct radeon_ring *ring = &rdev->ring[ib->ring]; in cik_sdma_ring_ib_execute() local
144 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in cik_sdma_ring_ib_execute()
145 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); in cik_sdma_ring_ib_execute()
171 struct radeon_ring *ring = &rdev->ring[ridx]; in cik_sdma_hdp_flush_ring_emit() local
202 struct radeon_ring *ring = &rdev->ring[fence->ring]; in cik_sdma_fence_ring_emit() local
374 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in cik_sdma_gfx_resume()
378 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in cik_sdma_gfx_resume()
410 ring->wptr = 0; in cik_sdma_gfx_resume()
423 ring->ready = true; in cik_sdma_gfx_resume()
425 r = radeon_ring_test(rdev, ring->idx, ring); in cik_sdma_gfx_resume()
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| H A D | ni_dma.c | 101 struct radeon_ring *ring) in cayman_dma_set_wptr() argument
124 struct radeon_ring *ring = &rdev->ring[ib->ring]; in cayman_dma_ring_ib_execute() local
133 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in cayman_dma_ring_ib_execute()
134 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); in cayman_dma_ring_ib_execute()
188 struct radeon_ring *ring; in cayman_dma_resume() local
196 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in cayman_dma_resume()
200 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in cayman_dma_resume()
242 ring->wptr = 0; in cayman_dma_resume()
247 ring->ready = true; in cayman_dma_resume()
249 r = radeon_ring_test(rdev, ring->idx, ring); in cayman_dma_resume()
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| H A D | radeon_trace.h | 34 __field(u32, ring)
40 __entry->ring = p->ring;
43 p->rdev, p->ring);
52 TP_ARGS(vmid, ring),
55 __field(u32, ring)
60 __entry->ring = ring;
118 __entry->ring = ring;
139 __entry->ring = ring;
181 __entry->ring = ring;
194 TP_ARGS(ring, sem)
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| /openbsd/sys/dev/pci/drm/i915/gt/ |
| H A D | intel_ring.c | 23 space = __intel_ring_space(ring->head, ring->emit, ring->size); in intel_ring_update_space()
73 intel_ring_reset(ring, ring->emit); in intel_ring_pin()
155 ring = kzalloc(sizeof(*ring), GFP_KERNEL); in intel_engine_create_ring()
156 if (!ring) in intel_engine_create_ring()
205 if (target->ring != ring) in wait_for_space()
210 ring->emit, ring->size)) in wait_for_space()
232 struct intel_ring *ring = rq->ring; in intel_ring_begin() local
246 const int remain_actual = ring->size - ring->emit; in intel_ring_begin()
291 GEM_BUG_ON(ring->emit + need_wrap > ring->size); in intel_ring_begin()
300 GEM_BUG_ON(ring->emit > ring->size - bytes); in intel_ring_begin()
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| H A D | intel_ring.h | 32 kref_get(&ring->ref); in intel_ring_get()
33 return ring; in intel_ring_get()
38 kref_put(&ring->ref, intel_ring_free); in intel_ring_put()
51 GEM_BUG_ON((rq->ring->vaddr + rq->ring->emit) != cs); in intel_ring_advance()
57 return pos & (ring->size - 1); in intel_ring_wrap()
63 typecheck(typeof(ring->size), next); in intel_ring_direction()
64 typecheck(typeof(ring->size), prev); in intel_ring_direction()
65 return (next - prev) << ring->wrap; in intel_ring_direction()
84 u32 offset = addr - rq->ring->vaddr; in intel_ring_offset()
86 GEM_BUG_ON(offset > rq->ring->size); in intel_ring_offset()
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