/openbsd/gnu/llvm/llvm/lib/Target/Sparc/ |
H A D | SparcInstrVIS.td | 30 let rd = 0, rs1 = 0, rs2 = 0 in 35 let rs2 = 0 in 175 "cmask8 $rs2", []>; 177 "cmask16 $rs2", []>; 179 "cmask32 $rs2", []>; 242 (ins I64Regs:$rs2), "lzcnt $rs2, $rd", []>; 246 (ins DFPRegs:$rs2), "movstosw $rs2, $rd", []>; 248 (ins DFPRegs:$rs2), "movstouw $rs2, $rd", []>; 250 (ins DFPRegs:$rs2), "movdtox $rs2, $rd", []>; 252 (ins I64Regs:$rs2), "movdtox $rs2, $rd", []>; [all …]
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H A D | SparcInstrAliases.td | 14 // mov<cond> <ccreg> rs2, rd 191 // t<cond> rs1 + rs2 => t<cond> %icc, rs1 + rs2 397 def : InstAlias<"tst $rs2", (ORCCrr G0, IntRegs:$rs2, G0)>; 482 def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>; 495 def : InstAlias<"mov $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>; 497 def : InstAlias<"mov $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>; 499 def : InstAlias<"mov $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>; 509 def : InstAlias<"wr $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>; 511 def : InstAlias<"wr $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>; 513 def : InstAlias<"wr $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>; [all …]
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H A D | SparcInstrInfo.td | 501 let rd = 0, rs1 = 0, rs2 = 0 in 1100 let rs2 = 0 in 1125 let rs2 = 0, rs1 = 5 in 1144 "wr $rs1, $rs2, %psr", []>; 1153 "wr $rs1, $rs2, %wim", []>; 1162 "wr $rs1, $rs2, %tbr", []>; 1189 let rs1 = 0, rs2 = 0 in 1198 "fitos $rs2, $rd", 1203 "fitod $rs2, $rd", 1727 "pwr $rs1, $rs2, %psr", []>; [all …]
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H A D | SparcInstr64Bit.td | 155 "andn $rs1, $rs2, $rd", 159 "orn $rs1, $rs2, $rd", 163 "xnor $rs1, $rs2, $rd", 197 "mulx $rs1, $rs2, $rd", 208 "sdivx $rs1, $rs2, $rd", 429 "fxtos $rs2, $rd", 433 "fxtod $rs2, $rd", 438 "fxtoq $rs2, $rd", 443 "fstox $rs2, $rd", 447 "fdtox $rs2, $rd", [all …]
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H A D | SparcInstrFormats.td | 127 bits<5> rs2; 134 let Inst{4-0} = rs2; 159 bits<5> rs2; 165 let Inst{4-0} = rs2; 172 bits<5> rs2; 186 bits<5> rs2; 200 bits<5> rs2; 257 bits<5> rs2; 289 bits<5> rs2; 304 bits<5> rs2; [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/CSKY/ |
H A D | CSKYInstrInfo16Instr.td | 521 def : Pat<(setne sGPR:$rs1, sGPR:$rs2), 523 def : Pat<(seteq sGPR:$rs1, sGPR:$rs2), 525 def : Pat<(setuge sGPR:$rs1, sGPR:$rs2), 527 def : Pat<(setule sGPR:$rs1, sGPR:$rs2), 529 def : Pat<(setult sGPR:$rs1, sGPR:$rs2), 531 def : Pat<(setugt sGPR:$rs1, sGPR:$rs2), 533 def : Pat<(setlt sGPR:$rs1, sGPR:$rs2), 535 def : Pat<(setgt sGPR:$rs1, sGPR:$rs2), 537 def : Pat<(setge sGPR:$rs1, sGPR:$rs2), 539 def : Pat<(setle sGPR:$rs1, sGPR:$rs2), [all …]
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H A D | CSKYInstrInfo.td | 1057 def : Pat<(Type (LoadOp (add GPR:$rs1, GPR:$rs2))), (Inst GPR:$rs1, GPR:$rs2, 0)>; 1058 def : Pat<(Type (LoadOp (add GPR:$rs1, (shl GPR:$rs2, (i32 1))))), (Inst GPR:$rs1, GPR:$rs2, 1)>; 1059 def : Pat<(Type (LoadOp (add GPR:$rs1, (shl GPR:$rs2, (i32 2))))), (Inst GPR:$rs1, GPR:$rs2, 2)>; 1060 def : Pat<(Type (LoadOp (add GPR:$rs1, (shl GPR:$rs2, (i32 3))))), (Inst GPR:$rs1, GPR:$rs2, 3)>; 1074 def : Pat<(StoreOp Type:$rs2, GPR:$rs1), (Inst Type:$rs2, GPR:$rs1, 0)>; 1089 def : Pat<(StoreOp Type:$rz, (add GPR:$rs1, GPR:$rs2)), (Inst Type:$rz, GPR:$rs1, GPR:$rs2, 0)>; 1191 def : Pat<(setne GPR:$rs1, GPR:$rs2), 1195 def : Pat<(setuge GPR:$rs1, GPR:$rs2), 1203 def : Pat<(setlt GPR:$rs1, GPR:$rs2), 1205 def : Pat<(setgt GPR:$rs1, GPR:$rs2), [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/RISCV/ |
H A D | RISCVInstrInfoVSDPatterns.td | 40 def : Pat<(store type:$rs2, GPR:$rs1), 59 def : Pat<(store type:$rs2, GPR:$rs1), 71 def : Pat<(store m.Mask:$rs2, GPR:$rs1), 85 (op_type op_reg_class:$rs2))), 88 op_reg_class:$rs2, 107 xop_kind:$rs2, 148 (xop_type xop_kind:$rs2), 789 def : Pat<(mti.Mask (and VR:$rs1, VR:$rs2)), 792 def : Pat<(mti.Mask (or VR:$rs1, VR:$rs2)), 795 def : Pat<(mti.Mask (xor VR:$rs1, VR:$rs2)), [all …]
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H A D | RISCVInstrInfoZb.td | 276 let rs2 = funct5; 525 def : Pat<(and GPR:$rs1, (not GPR:$rs2)), (ANDN GPR:$rs1, GPR:$rs2)>; 526 def : Pat<(or GPR:$rs1, (not GPR:$rs2)), (ORN GPR:$rs1, GPR:$rs2)>; 527 def : Pat<(xor GPR:$rs1, (not GPR:$rs2)), (XNOR GPR:$rs1, GPR:$rs2)>; 551 (BCLR GPR:$rs1, GPR:$rs2)>; 552 def : Pat<(and (rotl -2, GPR:$rs2), GPR:$rs1), (BCLR GPR:$rs1, GPR:$rs2)>; 554 (BSET GPR:$rs1, GPR:$rs2)>; 556 (BINV GPR:$rs1, GPR:$rs2)>; 558 (BEXT GPR:$rs1, GPR:$rs2)>; 560 def : Pat<(shiftop<shl> 1, GPR:$rs2), [all …]
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H A D | RISCVInstrInfoXVentana.td | 21 (ins GPR:$rs1, GPR:$rs2), opcodestr, 22 "$rd, $rs1, $rs2"> { 75 def : Pat<(i64 (select GPR:$rc, (and GPR:$rs1, GPR:$rs2), GPR:$rs1)), 76 (OR (AND $rs1, $rs2), (VT_MASKCN $rs1, $rc))>; 78 (OR (AND $rs1, $rs2), (VT_MASKC $rs1, $rc))>; 81 def : Pat<(i64 (select GPR:$rc, GPR:$rs1, GPR:$rs2)), 82 (OR (VT_MASKC $rs1, $rc), (VT_MASKCN $rs2, $rc))>; 98 (VT_MASKCN GPR:$rs2, (XORI GPR:$x, -2048)))>; 101 (VT_MASKCN GPR:$rs2, (XORI GPR:$x, -2048)))>; 105 (VT_MASKCN GPR:$rs2, (XOR GPR:$x, GPR:$y)))>; [all …]
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H A D | RISCVInstrInfoVVLPatterns.td | 498 xop_kind:$rs2, 771 fti.RegClass:$rs2, 946 (vti_m1.Vector VR:$rs2), 1113 (op vti.RegClass:$rs2, 1124 (op vti.RegClass:$rs2, 1554 vti.RegClass:$rs2, vti.RegClass:$rs2, vti.RegClass:$rs1, 1562 vti.RegClass:$rs2, vti.RegClass:$rs2, GPR:$rs1, 1570 vti.RegClass:$rs2, vti.RegClass:$rs2, simm5:$rs1, 1751 fvti.RegClass:$rs2, fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask V0), 1759 fvti.RegClass:$rs2, fvti.RegClass:$rs2, [all …]
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H A D | RISCVInstrInfoC.td | 290 OpcodeStr, "$rd, $rs2"> { 539 let rs2 = 0; 552 isCall=1, Defs=[X1], rs2 = 0 in 724 def : InstAlias<"c.sw $rs2, (${rs1})", (C_SW GPRC:$rs2, GPRCMem:$rs1, 0)>; 726 def : InstAlias<"c.swsp $rs2, (${rs1})", (C_SWSP GPRC:$rs2, SPMem:$rs1, 0)>; 731 def : InstAlias<"c.sd $rs2, (${rs1})", (C_SD GPRC:$rs2, GPRCMem:$rs1, 0)>; 733 def : InstAlias<"c.sdsp $rs2, (${rs1})", (C_SDSP GPRC:$rs2, SPMem:$rs1, 0)>; 738 def : InstAlias<"c.fsw $rs2, (${rs1})", (C_FSW FPR32C:$rs2, GPRCMem:$rs1, 0)>; 740 def : InstAlias<"c.fswsp $rs2, (${rs1})", (C_FSWSP FPR32C:$rs2, SPMem:$rs1, 0)>; 745 def : InstAlias<"c.fsd $rs2, (${rs1})", (C_FSD FPR64C:$rs2, GPRCMem:$rs1, 0)>; [all …]
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H A D | RISCVInstrInfoF.td | 203 (ins rty:$rs1, rty:$rs2), opcodestr, "$rd, $rs1, $rs2"> { 246 let rs2 = rs2val; 263 let rs2 = rs2val; 290 (ins rty:$rs1, rty:$rs2), opcodestr, "$rd, $rs1, $rs2"> { 425 def : InstAlias<"fsw $rs2, (${rs1})", (FSW FPR32:$rs2, GPR:$rs1, 0), 0>; 496 : Pat<(OpNode Ty:$rs1, Ty:$rs2, Cond), (Inst $rs1, $rs2)>; 500 : Pat<(OpNode RegTy:$rs1, RegTy:$rs2), (Inst $rs1, $rs2)>; 504 : Pat<(OpNode RegTy:$rs1, RegTy:$rs2), (Inst $rs1, $rs2, 0b111)>; 530 def : Pat<(fcopysign FPR32:$rs1, (fneg FPR32:$rs2)), (FSGNJN_S $rs1, $rs2)>; 532 // fmadd: rs1 * rs2 + rs3 [all …]
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H A D | RISCVInstrInfoZfh.td | 216 def : InstAlias<"fsh $rs2, (${rs1})", (FSH FPR16:$rs2, GPR:$rs1, 0), 0>; 279 def : Pat<(fcopysign FPR16:$rs1, (fneg FPR16:$rs2)), (FSGNJN_H $rs1, $rs2)>; 283 // fmadd: rs1 * rs2 + rs3 287 // fmsub: rs1 * rs2 - rs3 291 // fnmsub: -rs1 * rs2 + rs3 295 // fnmadd: -rs1 * rs2 - rs3 323 (AND (FLE_H $rs1, $rs2), 324 (FLE_H $rs2, $rs1))>; 326 (AND (FLE_H $rs1, $rs2), 367 def : Pat<(fcopysign FPR32:$rs1, FPR16:$rs2), (FSGNJ_S $rs1, (FCVT_S_H $rs2))>; [all …]
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H A D | RISCVInstrInfoD.td | 209 def : InstAlias<"fsd $rs2, (${rs1})", (FSD FPR64:$rs2, GPR:$rs1, 0), 0>; 278 def : Pat<(fcopysign FPR64:$rs1, (fneg FPR64:$rs2)), (FSGNJN_D $rs1, $rs2)>; 279 def : Pat<(fcopysign FPR64:$rs1, FPR32:$rs2), (FSGNJ_D $rs1, (FCVT_D_S $rs2))>; 280 def : Pat<(fcopysign FPR32:$rs1, FPR64:$rs2), (FSGNJ_S $rs1, (FCVT_S_D $rs2, 283 // fmadd: rs1 * rs2 + rs3 287 // fmsub: rs1 * rs2 - rs3 291 // fnmsub: -rs1 * rs2 + rs3 295 // fnmadd: -rs1 * rs2 - rs3 323 (AND (FLE_D $rs1, $rs2), 324 (FLE_D $rs2, $rs1))>; [all …]
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H A D | RISCVInstrInfoM.td | 96 (assertzexti32 GPR:$rs2)), 0xffffffff), 97 (DIVU GPR:$rs1, GPR:$rs2)>; 99 (assertzexti32 GPR:$rs2)), 0xffffffff), 100 (REMU GPR:$rs1, GPR:$rs2)>; 105 def : Pat<(srem (sexti32 (i64 GPR:$rs1)), (sexti32 (i64 GPR:$rs2))), 106 (REMW GPR:$rs1, GPR:$rs2)>; 114 def : Pat<(i64 (mul (and GPR:$rs1, 0xffffffff), (and GPR:$rs2, 0xffffffff))), 115 (MULHU (SLLI GPR:$rs1, 32), (SLLI GPR:$rs2, 32))>;
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H A D | RISCVInstrFormats.td | 266 bits<5> rs2; 282 bits<5> rs2; 299 bits<5> rs2; 317 bits<5> rs2; 334 bits<5> rs2; 396 bits<5> rs2; 411 bits<5> rs2; 459 bits<5> rs2; 480 bits<5> rs2; 519 bits<5> rs2; [all …]
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H A D | RISCVInstrInfo.td | 515 let rs2 = funct5; 581 (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2"> { 796 let rs2 = 0b00010; 802 let rs2 = 0b00010; 808 let rs2 = 0b00010; 815 let rs2 = 0b00101; 822 let rs2 = 0; 828 let rs2 = 0b00001; 866 let rs2 = 0b10010; 1177 : Pat<(OpNode GPR:$rs1, GPR:$rs2), (Inst GPR:$rs1, GPR:$rs2)>; [all …]
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H A D | RISCVInstrFormatsC.td | 40 bits<5> rs2; 44 let Inst{6-2} = rs2; 71 bits<5> rs2; 75 let Inst{6-2} = rs2; 111 bits<3> rs2; 116 let Inst{4-2} = rs2; 123 bits<3> rs2; 129 let Inst{4-2} = rs2;
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/openbsd/gnu/llvm/lldb/source/Plugins/Instruction/RISCV/ |
H A D | EmulateInstructionRISCV.cpp | 171 return rs1 == rs2; in CompareB() 173 return rs1 != rs2; in CompareB() 175 return int64_t(rs1) < int64_t(rs2); in CompareB() 177 return int64_t(rs1) >= int64_t(rs2); in CompareB() 179 return rs1 < rs2; in CompareB() 181 return rs1 >= rs2; in CompareB() 246 inst.rs2.Read(emulator), in Store() 247 [&](uint64_t rs2) { return emulator.WriteMem<T>(*addr, rs2); }) in Store() argument 275 auto [tmp, rs2] = tup; in AtomicSwap() 292 auto [tmp, rs2] = tup; in AtomicADD() [all …]
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/openbsd/sys/arch/m88k/m88k/ |
H A D | db_disasm.c | 384 u_int32_t rs2 = inst & 0x1f; in sindou() local 469 u_int32_t rs2 = inst & 0x1f; in jump() local 476 db_printf("\t\tr%d", rs2); in jump() 485 u_int32_t rs2 = inst & 0x1f; in instset() local 504 if (rs2 != 0) in instset() 505 db_printf("%d", rs2); in instset() 607 u_int32_t rs2 = inst & 0x1f; in bitman() local 676 u_int32_t rs2 = inst & 0x1f; in nimmem() local 736 db_printf("[r%d]", rs2); in nimmem() 738 db_printf(", r%d", rs2); in nimmem() [all …]
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H A D | m88110_fp.c | 225 u_int rf, rd, rs1, rs2, t1, t2, td, tmax, opcode; in m88110_fpu_emulate() local 236 rs2 = insn & 0x1f; in m88110_fpu_emulate() 323 m88110_fpu_fetch(frame, rs2, t2, tmax, &arg2); in m88110_fpu_emulate() 337 m88110_fpu_fetch(frame, rs2, t2, tmax, &dest); in m88110_fpu_emulate() 342 m88110_fpu_fetch(frame, rs2, FTYPE_INT, td, &dest); in m88110_fpu_emulate() 349 m88110_fpu_fetch(frame, rs2, t2, tmax, &arg2); in m88110_fpu_emulate() 364 m88110_fpu_fetch(frame, rs2, t2, tmax, &arg2); in m88110_fpu_emulate() 379 m88110_fpu_fetch(frame, rs2, t2, tmax, &arg2); in m88110_fpu_emulate() 385 m88110_fpu_fetch(frame, rs2, t2, t2, &dest); in m88110_fpu_emulate() 404 m88110_fpu_fetch(frame, rs2, t2, tmax, &arg2); in m88110_fpu_emulate() [all …]
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/openbsd/sys/arch/sparc64/fpu/ |
H A D | fpu.c | 604 fpu_explode(fe, &fe->fe_f2, rtype, rs2); in fpu_insn_fcmp() 633 int opf = instr.i_opf.i_opf, rd, rtype, rs1, rs2; in fpu_insn_fmul() local 646 fpu_explode(fe, &fe->fe_f2, rtype, rs2); in fpu_insn_fmul() 676 fpu_explode(fe, &fe->fe_f2, rstype, rs2); in fpu_insn_fmulx() 692 int opf = instr.i_opf.i_opf, rd, rtype, rs1, rs2; in fpu_insn_fdiv() local 705 fpu_explode(fe, &fe->fe_f2, rtype, rs2); in fpu_insn_fdiv() 721 int opf = instr.i_opf.i_opf, rd, rtype, rs1, rs2; in fpu_insn_fadd() local 734 fpu_explode(fe, &fe->fe_f2, rtype, rs2); in fpu_insn_fadd() 750 int opf = instr.i_opf.i_opf, rd, rtype, rs1, rs2; in fpu_insn_fsub() local 763 fpu_explode(fe, &fe->fe_f2, rtype, rs2); in fpu_insn_fsub() [all …]
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/openbsd/sys/arch/sparc64/include/ |
H A D | instr.h | 352 #define _I_OP3_LS_RAR(rd, op3, rs1, asi, rs2) \ argument 353 _I_OP3_GEN(IOP_mem, rd, op3, rs1, (asi) << 5 | (rs2)) 356 #define _I_OP3_LS_RR(rd, op3, rs1, rs2) \ argument 357 _I_OP3_GEN(IOP_mem, rd, op3, rs1, rs2) 358 #define _I_OP3_R_RAR(rd, op3, rs1, asi, rs2) \ argument 359 _I_OP3_GEN(IOP_reg, rd, op3, rs1, (asi) << 5 | (rs2)) 362 #define _I_OP3_R_RR(rd, op3, rs1, rs2) \ argument 363 _I_OP3_GEN(IOP_reg, rd, op3, rs1, rs2) 391 #define I_ORrr(rd, rs1, rs2) _I_OP3_R_RR(rd, IOP3_OR, rs1, rs2) argument 399 #define I_JMPLrr(rd, rs1, rs2) _I_OP3_R_RR(rd, IOP3_JMPL, rs1, rs2) argument
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/openbsd/gnu/usr.bin/gcc/gcc/testsuite/gcc.c-torture/execute/ |
H A D | 20021024-1.c | 14 unsigned rs1, rs2, rd; in bar() local 17 rs2 = (rop >> 23) & 0x1ff; in bar() 22 m = r[rs1] + r[rs2]; in bar()
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