1 /* $OpenBSD: scif.c,v 1.24 2024/11/05 18:58:59 miod Exp $ */
2 /* $NetBSD: scif.c,v 1.47 2006/07/23 22:06:06 ad Exp $ */
3
4 /*-
5 * Copyright (C) 1999 T.Horiuchi and SAITOH Masanobu. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30 /*-
31 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
32 * All rights reserved.
33 *
34 * This code is derived from software contributed to The NetBSD Foundation
35 * by Charles M. Hannum.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
39 * are met:
40 * 1. Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * 2. Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in the
44 * documentation and/or other materials provided with the distribution.
45 *
46 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
47 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
48 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
49 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
50 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
51 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
52 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
53 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
54 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
55 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
56 * POSSIBILITY OF SUCH DAMAGE.
57 */
58
59 /*
60 * Copyright (c) 1991 The Regents of the University of California.
61 * All rights reserved.
62 *
63 * Redistribution and use in source and binary forms, with or without
64 * modification, are permitted provided that the following conditions
65 * are met:
66 * 1. Redistributions of source code must retain the above copyright
67 * notice, this list of conditions and the following disclaimer.
68 * 2. Redistributions in binary form must reproduce the above copyright
69 * notice, this list of conditions and the following disclaimer in the
70 * documentation and/or other materials provided with the distribution.
71 * 3. Neither the name of the University nor the names of its contributors
72 * may be used to endorse or promote products derived from this software
73 * without specific prior written permission.
74 *
75 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
76 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
77 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
78 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
79 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
80 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
81 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
82 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
83 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
84 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
85 * SUCH DAMAGE.
86 *
87 * @(#)com.c 7.5 (Berkeley) 5/16/91
88 */
89
90 /*
91 * SH internal serial driver
92 *
93 * This code is derived from both z8530tty.c and com.c
94 */
95
96 #include <sys/param.h>
97 #include <sys/systm.h>
98 #include <sys/tty.h>
99 #include <sys/proc.h>
100 #include <sys/conf.h>
101 #include <sys/syslog.h>
102 #include <sys/kernel.h>
103 #include <sys/device.h>
104 #include <sys/malloc.h>
105 #include <sys/timeout.h>
106
107 #include <dev/cons.h>
108
109 #include <sh/clock.h>
110 #include <sh/trap.h>
111 #include <machine/intr.h>
112 #include <machine/conf.h>
113
114 #include <sh/dev/scifreg.h>
115
116 #ifdef DDB
117 #include <ddb/db_var.h>
118 #endif
119
120 void scifstart(struct tty *);
121 int scifparam(struct tty *, struct termios *);
122
123 cons_decl(scif);
124 void scif_intr_init(void);
125 int scifintr(void *);
126
127 struct scif_softc {
128 struct device sc_dev; /* boilerplate */
129 struct tty *sc_tty;
130 void *sc_si;
131
132 struct timeout sc_diag_tmo;
133
134 #if 0
135 bus_space_tag_t sc_iot; /* ISA i/o space identifier */
136 bus_space_handle_t sc_ioh; /* ISA io handle */
137
138 int sc_drq;
139
140 int sc_frequency;
141 #endif
142
143 u_int sc_overflows,
144 sc_floods,
145 sc_errors; /* number of retries so far */
146 u_char sc_status[7]; /* copy of registers */
147
148 int sc_hwflags;
149 int sc_swflags;
150 u_int sc_fifolen;
151
152 u_int sc_r_hiwat,
153 sc_r_lowat;
154 u_char *volatile sc_rbget,
155 *volatile sc_rbput;
156 volatile u_int sc_rbavail;
157 u_char *sc_rbuf,
158 *sc_ebuf;
159
160 u_char *sc_tba; /* transmit buffer address */
161 u_int sc_tbc, /* transmit byte count */
162 sc_heldtbc;
163
164 volatile u_char sc_rx_flags,
165 #define RX_TTY_BLOCKED 0x01
166 #define RX_TTY_OVERFLOWED 0x02
167 #define RX_IBUF_BLOCKED 0x04
168 #define RX_IBUF_OVERFLOWED 0x08
169 #define RX_ANY_BLOCK 0x0f
170 sc_tx_busy, /* working on an output chunk */
171 sc_tx_done, /* done with one output chunk */
172 sc_tx_stopped, /* H/W level stop (lost CTS) */
173 sc_st_check, /* got a status interrupt */
174 sc_rx_ready;
175
176 volatile u_char sc_heldchange;
177 };
178
179 /* controller driver configuration */
180 int scif_match(struct device *, void *, void *);
181 void scif_attach(struct device *, struct device *, void *);
182
183 void scif_break(struct scif_softc *, int);
184 void scif_iflush(struct scif_softc *);
185
186 void scifsoft(void *);
187 void scif_rxsoft(struct scif_softc *, struct tty *);
188 void scif_txsoft(struct scif_softc *, struct tty *);
189 void scif_stsoft(struct scif_softc *, struct tty *);
190 void scif_schedrx(struct scif_softc *);
191 void scifdiag(void *);
192
193
194 #define SCIFUNIT_MASK 0x7ffff
195 #define SCIFDIALOUT_MASK 0x80000
196
197 #define SCIFUNIT(x) (minor(x) & SCIFUNIT_MASK)
198 #define SCIFDIALOUT(x) (minor(x) & SCIFDIALOUT_MASK)
199
200 /* Hardware flag masks */
201 #define SCIF_HW_NOIEN 0x01
202 #define SCIF_HW_FIFO 0x02
203 #define SCIF_HW_FLOW 0x08
204 #define SCIF_HW_DEV_OK 0x20
205 #define SCIF_HW_CONSOLE 0x40
206
207 /* Buffer size for character buffer */
208 #define SCIF_RING_SIZE 2048
209
210 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */
211 u_int scif_rbuf_hiwat = (SCIF_RING_SIZE * 1) / 4;
212 u_int scif_rbuf_lowat = (SCIF_RING_SIZE * 3) / 4;
213
214 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */
215 int scifconscflag = CONMODE;
216 int scifisconsole = 0;
217
218 #ifdef SCIFCN_SPEED
219 unsigned int scifcn_speed = SCIFCN_SPEED;
220 #else
221 unsigned int scifcn_speed = 9600;
222 #endif
223
224 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */
225
226 u_int scif_rbuf_size = SCIF_RING_SIZE;
227
228 const struct cfattach scif_ca = {
229 sizeof(struct scif_softc), scif_match, scif_attach
230 };
231
232 struct cfdriver scif_cd = {
233 NULL, "scif", DV_DULL
234 };
235
236 static int scif_attached;
237
238 void InitializeScif(unsigned int);
239
240 /*
241 * following functions are for debugging purposes only
242 */
243 #define CR 0x0D
244 #define USART_ON (unsigned int)~0x08
245
246 void scif_putc(unsigned char);
247 unsigned char scif_getc(void);
248 int ScifErrCheck(void);
249
250
251 /* XXX: uwe
252 * Prepare for bus_spacification. The difference in access widths is
253 * still handled by the magic definitions in scifreg.h
254 */
255 #define scif_smr_read() SHREG_SCSMR2
256 #define scif_smr_write(v) (SHREG_SCSMR2 = (v))
257
258 #define scif_brr_read() SHREG_SCBRR2
259 #define scif_brr_write(v) (SHREG_SCBRR2 = (v))
260
261 #define scif_scr_read() SHREG_SCSCR2
262 #define scif_scr_write(v) (SHREG_SCSCR2 = (v))
263
264 #define scif_ftdr_write(v) (SHREG_SCFTDR2 = (v))
265
266 #define scif_ssr_read() SHREG_SCSSR2
267 #define scif_ssr_write(v) (SHREG_SCSSR2 = (v))
268
269 #define scif_frdr_read() SHREG_SCFRDR2
270
271 #define scif_fcr_read() SHREG_SCFCR2
272 #define scif_fcr_write(v) (SHREG_SCFCR2 = (v))
273
274 #define scif_fdr_read() SHREG_SCFDR2
275
276 #ifdef SH4 /* additional registers in sh4 */
277
278 #define scif_sptr_read() SHREG_SCSPTR2
279 #define scif_sptr_write(v) (SHREG_SCSPTR2 = (v))
280
281 #define scif_lsr_read() SHREG_SCLSR2
282 #define scif_lsr_write(v) (SHREG_SCLSR2 = (v))
283
284 #endif /* SH4 */
285
286
287 /*
288 * InitializeScif
289 * : unsigned int bps;
290 * : SCIF(Serial Communication Interface)
291 */
292
293 void
InitializeScif(unsigned int bps)294 InitializeScif(unsigned int bps)
295 {
296 /* Initialize SCR */
297 scif_scr_write(0x00);
298
299 #if 0
300 scif_fcr_write(SCFCR2_TFRST | SCFCR2_RFRST | SCFCR2_MCE);
301 #else
302 scif_fcr_write(SCFCR2_TFRST | SCFCR2_RFRST);
303 #endif
304 /* Serial Mode Register */
305 scif_smr_write(0x00); /* 8bit,NonParity,Even,1Stop */
306
307 /* Bit Rate Register */
308 scif_brr_write(divrnd(sh_clock_get_pclock(), 32 * bps) - 1);
309
310 /*
311 * wait 2m Sec, because Send/Recv must begin 1 bit period after
312 * BRR is set.
313 */
314 delay(2000);
315
316 #if 0
317 scif_fcr_write(FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1 | SCFCR2_MCE);
318 #else
319 scif_fcr_write(FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1);
320 #endif
321
322 /* Send permission, Receive permission ON */
323 scif_scr_write(SCSCR2_TE | SCSCR2_RE);
324
325 /* Serial Status Register */
326 scif_ssr_write(scif_ssr_read() & SCSSR2_TDFE); /* Clear Status */
327 }
328
329
330 /*
331 * scif_putc
332 * : unsigned char c;
333 */
334
335 void
scif_putc(unsigned char c)336 scif_putc(unsigned char c)
337 {
338 /* wait for ready */
339 while ((scif_fdr_read() & SCFDR2_TXCNT) == SCFDR2_TXF_FULL)
340 continue;
341
342 /* write send data to send register */
343 scif_ftdr_write(c);
344
345 /* clear ready flag */
346 scif_ssr_write(scif_ssr_read() & ~(SCSSR2_TDFE | SCSSR2_TEND));
347 }
348
349 /*
350 * : ScifErrCheck
351 * 0x80 = error
352 * 0x08 = frame error
353 * 0x04 = parity error
354 */
355 int
ScifErrCheck(void)356 ScifErrCheck(void)
357 {
358 return (scif_ssr_read() & (SCSSR2_ER | SCSSR2_FER | SCSSR2_PER));
359 }
360
361 /*
362 * scif_getc
363 */
364 unsigned char
scif_getc(void)365 scif_getc(void)
366 {
367 unsigned char c, err_c;
368 #ifdef SH4
369 unsigned short err_c2 = 0; /* XXXGCC: -Wuninitialized */
370 #endif
371
372 for (;;) {
373 /* wait for ready */
374 while ((scif_fdr_read() & SCFDR2_RECVCNT) == 0)
375 continue;
376
377 c = scif_frdr_read();
378 err_c = scif_ssr_read();
379 scif_ssr_write(scif_ssr_read()
380 & ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_RDF | SCSSR2_DR));
381 #ifdef SH4
382 if (CPU_IS_SH4) {
383 err_c2 = scif_lsr_read();
384 scif_lsr_write(scif_lsr_read() & ~SCLSR2_ORER);
385 }
386 #endif
387 if ((err_c & (SCSSR2_ER | SCSSR2_BRK | SCSSR2_FER
388 | SCSSR2_PER)) == 0) {
389 #ifdef SH4
390 if (CPU_IS_SH4 && ((err_c2 & SCLSR2_ORER) == 0))
391 #endif
392 return(c);
393 }
394 }
395
396 }
397
398 int
scif_match(struct device * parent,void * vcf,void * aux)399 scif_match(struct device *parent, void *vcf, void *aux)
400 {
401 if (scif_attached != 0)
402 return 0;
403
404 return 1;
405 }
406
407 void
scif_attach(struct device * parent,struct device * self,void * aux)408 scif_attach(struct device *parent, struct device *self, void *aux)
409 {
410 struct scif_softc *sc = (struct scif_softc *)self;
411 struct tty *tp;
412
413 scif_attached = 1;
414
415 sc->sc_hwflags = 0; /* XXX */
416 sc->sc_swflags = 0; /* XXX */
417 sc->sc_fifolen = 16;
418
419 if (scifisconsole) {
420 /* InitializeScif(scifcn_speed); */
421 SET(sc->sc_hwflags, SCIF_HW_CONSOLE);
422 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR);
423 printf("\n%s: console\n", sc->sc_dev.dv_xname);
424 } else {
425 InitializeScif(9600);
426 printf("\n");
427 }
428
429 timeout_set(&sc->sc_diag_tmo, scifdiag, sc);
430 #ifdef SH4
431 intc_intr_establish(SH4_INTEVT_SCIF_ERI, IST_LEVEL, IPL_TTY,
432 scifintr, sc, self->dv_xname);
433 intc_intr_establish(SH4_INTEVT_SCIF_RXI, IST_LEVEL, IPL_TTY,
434 scifintr, sc, self->dv_xname);
435 intc_intr_establish(SH4_INTEVT_SCIF_BRI, IST_LEVEL, IPL_TTY,
436 scifintr, sc, self->dv_xname);
437 intc_intr_establish(SH4_INTEVT_SCIF_TXI, IST_LEVEL, IPL_TTY,
438 scifintr, sc, self->dv_xname);
439 #else
440 intc_intr_establish(SH7709_INTEVT2_SCIF_ERI, IST_LEVEL, IPL_TTY,
441 scifintr, sc, self->dv_xname);
442 intc_intr_establish(SH7709_INTEVT2_SCIF_RXI, IST_LEVEL, IPL_TTY,
443 scifintr, sc, self->dv_xname);
444 intc_intr_establish(SH7709_INTEVT2_SCIF_BRI, IST_LEVEL, IPL_TTY,
445 scifintr, sc, self->dv_xname);
446 intc_intr_establish(SH7709_INTEVT2_SCIF_TXI, IST_LEVEL, IPL_TTY,
447 scifintr, sc, self->dv_xname);
448 #endif
449
450 sc->sc_si = softintr_establish(IPL_SOFTSERIAL, scifsoft, sc);
451 SET(sc->sc_hwflags, SCIF_HW_DEV_OK);
452
453 tp = ttymalloc(0);
454 tp->t_oproc = scifstart;
455 tp->t_param = scifparam;
456 tp->t_hwiflow = NULL;
457
458 sc->sc_tty = tp;
459 sc->sc_rbuf = malloc(scif_rbuf_size << 1, M_DEVBUF, M_NOWAIT);
460 if (sc->sc_rbuf == NULL) {
461 printf("%s: unable to allocate ring buffer\n",
462 sc->sc_dev.dv_xname);
463 return;
464 }
465 sc->sc_ebuf = sc->sc_rbuf + (scif_rbuf_size << 1);
466 }
467
468 /*
469 * Start or restart transmission.
470 */
471 void
scifstart(struct tty * tp)472 scifstart(struct tty *tp)
473 {
474 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)];
475 int s;
476
477 s = spltty();
478 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP))
479 goto out;
480 if (sc->sc_tx_stopped)
481 goto out;
482
483 ttwakeupwr(tp);
484 if (tp->t_outq.c_cc == 0)
485 goto out;
486
487 /* Grab the first contiguous region of buffer space. */
488 {
489 u_char *tba;
490 int tbc;
491
492 tba = tp->t_outq.c_cf;
493 tbc = ndqb(&tp->t_outq, 0);
494
495
496 sc->sc_tba = tba;
497 sc->sc_tbc = tbc;
498 }
499
500 SET(tp->t_state, TS_BUSY);
501 sc->sc_tx_busy = 1;
502
503 /* Enable transmit completion interrupts if necessary. */
504 scif_scr_write(scif_scr_read() | SCSCR2_TIE | SCSCR2_RIE);
505
506 /* Output the first chunk of the contiguous buffer. */
507 {
508 int n;
509 int maxchars;
510 int i;
511
512 n = sc->sc_tbc;
513 maxchars = sc->sc_fifolen
514 - ((scif_fdr_read() & SCFDR2_TXCNT) >> 8);
515 if (n > maxchars)
516 n = maxchars;
517
518 for (i = 0; i < n; i++) {
519 scif_putc(*(sc->sc_tba));
520 sc->sc_tba++;
521 }
522 sc->sc_tbc -= n;
523 }
524 out:
525 splx(s);
526 return;
527 }
528
529 /*
530 * Set SCIF tty parameters from termios.
531 * XXX - Should just copy the whole termios after
532 * making sure all the changes could be done.
533 */
534 int
scifparam(struct tty * tp,struct termios * t)535 scifparam(struct tty *tp, struct termios *t)
536 {
537 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)];
538 int ospeed = t->c_ospeed;
539 int s;
540
541 /* Check requested parameters. */
542 if (ospeed < 0)
543 return (EINVAL);
544 if (t->c_ispeed && t->c_ispeed != t->c_ospeed)
545 return (EINVAL);
546
547 /*
548 * For the console, always force CLOCAL and !HUPCL, so that the port
549 * is always active.
550 */
551 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) ||
552 ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) {
553 SET(t->c_cflag, CLOCAL);
554 CLR(t->c_cflag, HUPCL);
555 }
556
557 /*
558 * If there were no changes, don't do anything. This avoids dropping
559 * input and improves performance when all we did was frob things like
560 * VMIN and VTIME.
561 */
562 if (tp->t_ospeed == t->c_ospeed &&
563 tp->t_cflag == t->c_cflag)
564 return (0);
565
566 #if 0
567 /* XXX (msaitoh) */
568 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag);
569 #endif
570
571 s = spltty();
572
573 /*
574 * Set the flow control pins depending on the current flow control
575 * mode.
576 */
577 if (ISSET(t->c_cflag, CRTSCTS)) {
578 scif_fcr_write(scif_fcr_read() | SCFCR2_MCE);
579 } else {
580 scif_fcr_write(scif_fcr_read() & ~SCFCR2_MCE);
581 }
582
583 scif_brr_write(divrnd(sh_clock_get_pclock(), 32 * ospeed) -1);
584
585 /*
586 * Set the FIFO threshold based on the receive speed.
587 *
588 * * If it's a low speed, it's probably a mouse or some other
589 * interactive device, so set the threshold low.
590 * * If it's a high speed, trim the trigger level down to prevent
591 * overflows.
592 * * Otherwise set it a bit higher.
593 */
594 #if 0
595 /* XXX (msaitoh) */
596 if (ISSET(sc->sc_hwflags, SCIF_HW_HAYESP))
597 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8;
598 else if (ISSET(sc->sc_hwflags, SCIF_HW_FIFO))
599 sc->sc_fifo = FIFO_ENABLE |
600 (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 :
601 t->c_ospeed <= 38400 ? FIFO_TRIGGER_8 : FIFO_TRIGGER_4);
602 else
603 sc->sc_fifo = 0;
604 #endif
605
606 /* And copy to tty. */
607 tp->t_ispeed = 0;
608 tp->t_ospeed = t->c_ospeed;
609 tp->t_cflag = t->c_cflag;
610
611 if (!sc->sc_heldchange) {
612 if (sc->sc_tx_busy) {
613 sc->sc_heldtbc = sc->sc_tbc;
614 sc->sc_tbc = 0;
615 sc->sc_heldchange = 1;
616 }
617 #if 0
618 /* XXX (msaitoh) */
619 else
620 scif_loadchannelregs(sc);
621 #endif
622 }
623
624 if (!ISSET(t->c_cflag, CHWFLOW)) {
625 /* Disable the high water mark. */
626 sc->sc_r_hiwat = 0;
627 sc->sc_r_lowat = 0;
628 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) {
629 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED);
630 scif_schedrx(sc);
631 }
632 } else {
633 sc->sc_r_hiwat = scif_rbuf_hiwat;
634 sc->sc_r_lowat = scif_rbuf_lowat;
635 }
636
637 splx(s);
638
639 #ifdef SCIF_DEBUG
640 if (scif_debug)
641 scifstatus(sc, "scifparam ");
642 #endif
643
644 if (!ISSET(t->c_cflag, CHWFLOW)) {
645 if (sc->sc_tx_stopped) {
646 sc->sc_tx_stopped = 0;
647 scifstart(tp);
648 }
649 }
650
651 return (0);
652 }
653
654 void
scif_iflush(struct scif_softc * sc)655 scif_iflush(struct scif_softc *sc)
656 {
657 int i;
658 unsigned char c;
659
660 i = scif_fdr_read() & SCFDR2_RECVCNT;
661
662 while (i > 0) {
663 c = scif_frdr_read();
664 scif_ssr_write(scif_ssr_read() & ~(SCSSR2_RDF | SCSSR2_DR));
665 i--;
666 }
667 }
668
669 int
scifopen(dev_t dev,int flag,int mode,struct proc * p)670 scifopen(dev_t dev, int flag, int mode, struct proc *p)
671 {
672 int unit = SCIFUNIT(dev);
673 struct scif_softc *sc;
674 struct tty *tp;
675 int s;
676 int error;
677
678 if (unit >= scif_cd.cd_ndevs)
679 return (ENXIO);
680 sc = scif_cd.cd_devs[unit];
681 if (sc == 0 || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK) ||
682 sc->sc_rbuf == NULL)
683 return (ENXIO);
684
685 tp = sc->sc_tty;
686
687 if (ISSET(tp->t_state, TS_ISOPEN) &&
688 ISSET(tp->t_state, TS_XCLUDE) &&
689 suser(p) != 0)
690 return (EBUSY);
691
692 s = spltty();
693
694 /*
695 * Do the following iff this is a first open.
696 */
697 if (!ISSET(tp->t_state, TS_ISOPEN)) {
698 struct termios t;
699
700 tp->t_dev = dev;
701
702
703 /* Turn on interrupts. */
704 scif_scr_write(scif_scr_read() | SCSCR2_TIE | SCSCR2_RIE);
705
706 /*
707 * Initialize the termios status to the defaults. Add in the
708 * sticky bits from TIOCSFLAGS.
709 */
710 t.c_ispeed = 0;
711 if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) {
712 t.c_ospeed = scifcn_speed; /* XXX (msaitoh) */
713 t.c_cflag = scifconscflag;
714 } else {
715 t.c_ospeed = TTYDEF_SPEED;
716 t.c_cflag = TTYDEF_CFLAG;
717 }
718 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL))
719 SET(t.c_cflag, CLOCAL);
720 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS))
721 SET(t.c_cflag, CRTSCTS);
722 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF))
723 SET(t.c_cflag, MDMBUF);
724 /* Make sure scifparam() will do something. */
725 tp->t_ospeed = 0;
726 (void) scifparam(tp, &t);
727
728 /*
729 * XXX landisk has no hardware flow control!
730 * When porting to another platform, fix this somehow
731 */
732 SET(tp->t_state, TS_CARR_ON);
733
734 tp->t_iflag = TTYDEF_IFLAG;
735 tp->t_oflag = TTYDEF_OFLAG;
736 tp->t_lflag = TTYDEF_LFLAG;
737 ttychars(tp);
738 ttsetwater(tp);
739
740 /* Clear the input ring, and unblock. */
741 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf;
742 sc->sc_rbavail = scif_rbuf_size;
743 scif_iflush(sc);
744 CLR(sc->sc_rx_flags, RX_ANY_BLOCK);
745 #if 0
746 /* XXX (msaitoh) */
747 scif_hwiflow(sc);
748 #endif
749
750 #ifdef SCIF_DEBUG
751 if (scif_debug)
752 scifstatus(sc, "scifopen ");
753 #endif
754
755 }
756
757 splx(s);
758
759 error = (*linesw[tp->t_line].l_open)(dev, tp, p);
760 if (error)
761 goto bad;
762
763 return (0);
764
765 bad:
766
767 return (error);
768 }
769
770 int
scifclose(dev_t dev,int flag,int mode,struct proc * p)771 scifclose(dev_t dev, int flag, int mode, struct proc *p)
772 {
773 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
774 struct tty *tp = sc->sc_tty;
775
776 /* XXX This is for cons.c. */
777 if (!ISSET(tp->t_state, TS_ISOPEN))
778 return (0);
779
780 (*linesw[tp->t_line].l_close)(tp, flag, p);
781 ttyclose(tp);
782
783 return (0);
784 }
785
786 int
scifread(dev_t dev,struct uio * uio,int flag)787 scifread(dev_t dev, struct uio *uio, int flag)
788 {
789 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
790 struct tty *tp = sc->sc_tty;
791
792 return ((*linesw[tp->t_line].l_read)(tp, uio, flag));
793 }
794
795 int
scifwrite(dev_t dev,struct uio * uio,int flag)796 scifwrite(dev_t dev, struct uio *uio, int flag)
797 {
798 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
799 struct tty *tp = sc->sc_tty;
800
801 return ((*linesw[tp->t_line].l_write)(tp, uio, flag));
802 }
803
804 struct tty *
sciftty(dev_t dev)805 sciftty(dev_t dev)
806 {
807 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
808 struct tty *tp = sc->sc_tty;
809
810 return (tp);
811 }
812
813 int
scifioctl(dev_t dev,u_long cmd,caddr_t data,int flag,struct proc * p)814 scifioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p)
815 {
816 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
817 struct tty *tp = sc->sc_tty;
818 int error;
819 int s;
820
821 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
822 if (error != -1)
823 return (error);
824
825 error = ttioctl(tp, cmd, data, flag, p);
826 if (error != -1)
827 return (error);
828
829 error = 0;
830
831 s = spltty();
832
833 switch (cmd) {
834 case TIOCSBRK:
835 scif_break(sc, 1);
836 break;
837
838 case TIOCCBRK:
839 scif_break(sc, 0);
840 break;
841
842 case TIOCGFLAGS:
843 *(int *)data = sc->sc_swflags;
844 break;
845
846 case TIOCSFLAGS:
847 error = suser(p);
848 if (error)
849 break;
850 sc->sc_swflags = *(int *)data;
851 break;
852
853 default:
854 error = -1;
855 break;
856 }
857
858 splx(s);
859
860 return (error);
861 }
862
863 void
scif_schedrx(struct scif_softc * sc)864 scif_schedrx(struct scif_softc *sc)
865 {
866 sc->sc_rx_ready = 1;
867
868 /* Wake up the poller. */
869 softintr_schedule(sc->sc_si);
870 }
871
872 void
scif_break(struct scif_softc * sc,int onoff)873 scif_break(struct scif_softc *sc, int onoff)
874 {
875 if (onoff)
876 scif_ssr_write(scif_ssr_read() & ~SCSSR2_TDFE);
877 else
878 scif_ssr_write(scif_ssr_read() | SCSSR2_TDFE);
879
880 #if 0 /* XXX */
881 if (!sc->sc_heldchange) {
882 if (sc->sc_tx_busy) {
883 sc->sc_heldtbc = sc->sc_tbc;
884 sc->sc_tbc = 0;
885 sc->sc_heldchange = 1;
886 } else
887 scif_loadchannelregs(sc);
888 }
889 #endif
890 }
891
892 /*
893 * Stop output, e.g., for ^S or output flush.
894 */
895 int
scifstop(struct tty * tp,int flag)896 scifstop(struct tty *tp, int flag)
897 {
898 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)];
899 int s;
900
901 s = spltty();
902 if (ISSET(tp->t_state, TS_BUSY)) {
903 /* Stop transmitting at the next chunk. */
904 sc->sc_tbc = 0;
905 sc->sc_heldtbc = 0;
906 if (!ISSET(tp->t_state, TS_TTSTOP))
907 SET(tp->t_state, TS_FLUSH);
908 }
909 splx(s);
910 return (0);
911 }
912
913 void
scif_intr_init(void)914 scif_intr_init(void)
915 {
916 /* XXX */
917 }
918
919 void
scifdiag(void * arg)920 scifdiag(void *arg)
921 {
922 struct scif_softc *sc = arg;
923 int overflows, floods;
924 int s;
925
926 s = spltty();
927 overflows = sc->sc_overflows;
928 sc->sc_overflows = 0;
929 floods = sc->sc_floods;
930 sc->sc_floods = 0;
931 sc->sc_errors = 0;
932 splx(s);
933
934 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n",
935 sc->sc_dev.dv_xname,
936 overflows, overflows == 1 ? "" : "s",
937 floods, floods == 1 ? "" : "s");
938 }
939
940 void
scif_rxsoft(struct scif_softc * sc,struct tty * tp)941 scif_rxsoft(struct scif_softc *sc, struct tty *tp)
942 {
943 int (*rint)(int, struct tty *) = *linesw[tp->t_line].l_rint;
944 u_char *get, *end;
945 u_int cc, scc;
946 u_char ssr2;
947 int code;
948 int s;
949
950 end = sc->sc_ebuf;
951 get = sc->sc_rbget;
952 scc = cc = scif_rbuf_size - sc->sc_rbavail;
953
954 if (cc == scif_rbuf_size) {
955 sc->sc_floods++;
956 if (sc->sc_errors++ == 0)
957 timeout_add_sec(&sc->sc_diag_tmo, 60);
958 }
959
960 while (cc) {
961 code = get[0];
962 ssr2 = get[1];
963 if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER | SCSSR2_PER)) {
964 if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER))
965 SET(code, TTY_FE);
966 if (ISSET(ssr2, SCSSR2_PER))
967 SET(code, TTY_PE);
968 }
969 if ((*rint)(code, tp) == -1) {
970 /*
971 * The line discipline's buffer is out of space.
972 */
973 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) {
974 /*
975 * We're either not using flow control, or the
976 * line discipline didn't tell us to block for
977 * some reason. Either way, we have no way to
978 * know when there's more space available, so
979 * just drop the rest of the data.
980 */
981 get += cc << 1;
982 if (get >= end)
983 get -= scif_rbuf_size << 1;
984 cc = 0;
985 } else {
986 /*
987 * Don't schedule any more receive processing
988 * until the line discipline tells us there's
989 * space available (through scifhwiflow()).
990 * Leave the rest of the data in the input
991 * buffer.
992 */
993 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED);
994 }
995 break;
996 }
997 get += 2;
998 if (get >= end)
999 get = sc->sc_rbuf;
1000 cc--;
1001 }
1002
1003 if (cc != scc) {
1004 sc->sc_rbget = get;
1005 s = spltty();
1006 cc = sc->sc_rbavail += scc - cc;
1007 /* Buffers should be ok again, release possible block. */
1008 if (cc >= sc->sc_r_lowat) {
1009 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) {
1010 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED);
1011 scif_scr_write(scif_scr_read() | SCSCR2_RIE);
1012 }
1013 #if 0
1014 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) {
1015 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED);
1016 scif_hwiflow(sc);
1017 }
1018 #endif
1019 }
1020 splx(s);
1021 }
1022 }
1023
1024 void
scif_txsoft(struct scif_softc * sc,struct tty * tp)1025 scif_txsoft(struct scif_softc *sc, struct tty *tp)
1026 {
1027 CLR(tp->t_state, TS_BUSY);
1028 if (ISSET(tp->t_state, TS_FLUSH))
1029 CLR(tp->t_state, TS_FLUSH);
1030 else
1031 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf));
1032 (*linesw[tp->t_line].l_start)(tp);
1033 }
1034
1035 void
scif_stsoft(struct scif_softc * sc,struct tty * tp)1036 scif_stsoft(struct scif_softc *sc, struct tty *tp)
1037 {
1038 #if 0
1039 /* XXX (msaitoh) */
1040 u_char msr, delta;
1041 int s;
1042
1043 s = spltty();
1044 msr = sc->sc_msr;
1045 delta = sc->sc_msr_delta;
1046 sc->sc_msr_delta = 0;
1047 splx(s);
1048
1049 if (ISSET(delta, sc->sc_msr_dcd)) {
1050 /*
1051 * Inform the tty layer that carrier detect changed.
1052 */
1053 (void) (*linesw[tp->t_line].l_modem)(tp, ISSET(msr, MSR_DCD));
1054 }
1055
1056 if (ISSET(delta, sc->sc_msr_cts)) {
1057 /* Block or unblock output according to flow control. */
1058 if (ISSET(msr, sc->sc_msr_cts)) {
1059 sc->sc_tx_stopped = 0;
1060 (*linesw[tp->t_line].l_start)(tp);
1061 } else {
1062 sc->sc_tx_stopped = 1;
1063 }
1064 }
1065
1066 #ifdef SCIF_DEBUG
1067 if (scif_debug)
1068 scifstatus(sc, "scif_stsoft");
1069 #endif
1070 #endif
1071 }
1072
1073 void
scifsoft(void * arg)1074 scifsoft(void *arg)
1075 {
1076 struct scif_softc *sc = arg;
1077 struct tty *tp;
1078
1079 tp = sc->sc_tty;
1080
1081 if (sc->sc_rx_ready) {
1082 sc->sc_rx_ready = 0;
1083 scif_rxsoft(sc, tp);
1084 }
1085
1086 #if 0
1087 if (sc->sc_st_check) {
1088 sc->sc_st_check = 0;
1089 scif_stsoft(sc, tp);
1090 }
1091 #endif
1092
1093 if (sc->sc_tx_done) {
1094 sc->sc_tx_done = 0;
1095 scif_txsoft(sc, tp);
1096 }
1097 }
1098
1099 int
scifintr(void * arg)1100 scifintr(void *arg)
1101 {
1102 struct scif_softc *sc = arg;
1103 u_char *put, *end;
1104 u_int cc;
1105 u_short ssr2;
1106 int count;
1107
1108 end = sc->sc_ebuf;
1109 put = sc->sc_rbput;
1110 cc = sc->sc_rbavail;
1111
1112 do {
1113 ssr2 = scif_ssr_read();
1114 if (ISSET(ssr2, SCSSR2_BRK)) {
1115 scif_ssr_write(scif_ssr_read()
1116 & ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_DR));
1117 #ifdef DDB
1118 if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE) &&
1119 db_console != 0) {
1120 db_enter();
1121 }
1122 #endif /* DDB */
1123 }
1124 count = scif_fdr_read() & SCFDR2_RECVCNT;
1125 if (count != 0) {
1126 for (;;) {
1127 u_char c = scif_frdr_read();
1128 u_char err = (u_char)(scif_ssr_read() & 0x00ff);
1129
1130 scif_ssr_write(scif_ssr_read()
1131 & ~(SCSSR2_ER | SCSSR2_RDF | SCSSR2_DR));
1132 #ifdef SH4
1133 if (CPU_IS_SH4)
1134 scif_lsr_write(scif_lsr_read()
1135 & ~SCLSR2_ORER);
1136 #endif
1137 if ((cc > 0) && (count > 0)) {
1138 put[0] = c;
1139 put[1] = err;
1140 put += 2;
1141 if (put >= end)
1142 put = sc->sc_rbuf;
1143 cc--;
1144 count--;
1145 } else
1146 break;
1147 }
1148
1149 /*
1150 * Current string of incoming characters ended because
1151 * no more data was available or we ran out of space.
1152 * Schedule a receive event if any data was received.
1153 * If we're out of space, turn off receive interrupts.
1154 */
1155 sc->sc_rbput = put;
1156 sc->sc_rbavail = cc;
1157 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED))
1158 sc->sc_rx_ready = 1;
1159
1160 /*
1161 * See if we are in danger of overflowing a buffer. If
1162 * so, use hardware flow control to ease the pressure.
1163 */
1164 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) &&
1165 cc < sc->sc_r_hiwat) {
1166 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED);
1167 #if 0
1168 scif_hwiflow(sc);
1169 #endif
1170 }
1171
1172 /*
1173 * If we're out of space, disable receive interrupts
1174 * until the queue has drained a bit.
1175 */
1176 if (!cc) {
1177 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED);
1178 scif_scr_write(scif_scr_read() & ~SCSCR2_RIE);
1179 }
1180 } else {
1181 if (scif_ssr_read() & (SCSSR2_RDF | SCSSR2_DR)) {
1182 scif_scr_write(scif_scr_read()
1183 & ~(SCSCR2_TIE | SCSCR2_RIE));
1184 delay(10);
1185 scif_scr_write(scif_scr_read()
1186 | SCSCR2_TIE | SCSCR2_RIE);
1187 continue;
1188 }
1189 }
1190 } while (scif_ssr_read() & (SCSSR2_RDF | SCSSR2_DR));
1191
1192 #if 0
1193 msr = bus_space_read_1(iot, ioh, scif_msr);
1194 delta = msr ^ sc->sc_msr;
1195 sc->sc_msr = msr;
1196 if (ISSET(delta, sc->sc_msr_mask)) {
1197 SET(sc->sc_msr_delta, delta);
1198
1199 /*
1200 * Pulse-per-second clock signal on edge of DCD?
1201 */
1202 if (ISSET(delta, sc->sc_ppsmask)) {
1203 struct timeval tv;
1204 if (ISSET(msr, sc->sc_ppsmask) ==
1205 sc->sc_ppsassert) {
1206 /* XXX nanotime() */
1207 microtime(&tv);
1208 TIMEVAL_TO_TIMESPEC(&tv,
1209 &sc->ppsinfo.assert_timestamp);
1210 if (sc->ppsparam.mode & PPS_OFFSETASSERT) {
1211 timespecadd(&sc->ppsinfo.assert_timestamp,
1212 &sc->ppsparam.assert_offset,
1213 &sc->ppsinfo.assert_timestamp);
1214 TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.assert_timestamp);
1215 }
1216
1217 #ifdef PPS_SYNC
1218 if (sc->ppsparam.mode & PPS_HARDPPSONASSERT)
1219 hardpps(&tv, tv.tv_usec);
1220 #endif
1221 sc->ppsinfo.assert_sequence++;
1222 sc->ppsinfo.current_mode =
1223 sc->ppsparam.mode;
1224
1225 } else if (ISSET(msr, sc->sc_ppsmask) ==
1226 sc->sc_ppsclear) {
1227 /* XXX nanotime() */
1228 microtime(&tv);
1229 TIMEVAL_TO_TIMESPEC(&tv,
1230 &sc->ppsinfo.clear_timestamp);
1231 if (sc->ppsparam.mode & PPS_OFFSETCLEAR) {
1232 timespecadd(&sc->ppsinfo.clear_timestamp,
1233 &sc->ppsparam.clear_offset,
1234 &sc->ppsinfo.clear_timestamp);
1235 TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.clear_timestamp);
1236 }
1237
1238 #ifdef PPS_SYNC
1239 if (sc->ppsparam.mode & PPS_HARDPPSONCLEAR)
1240 hardpps(&tv, tv.tv_usec);
1241 #endif
1242 sc->ppsinfo.clear_sequence++;
1243 sc->ppsinfo.current_mode =
1244 sc->ppsparam.mode;
1245 }
1246 }
1247
1248 /*
1249 * Stop output immediately if we lose the output
1250 * flow control signal or carrier detect.
1251 */
1252 if (ISSET(~msr, sc->sc_msr_mask)) {
1253 sc->sc_tbc = 0;
1254 sc->sc_heldtbc = 0;
1255 #ifdef SCIF_DEBUG
1256 if (scif_debug)
1257 scifstatus(sc, "scifintr ");
1258 #endif
1259 }
1260
1261 sc->sc_st_check = 1;
1262 }
1263 #endif
1264
1265 /*
1266 * Done handling any receive interrupts. See if data can be
1267 * transmitted as well. Schedule tx done event if no data left
1268 * and tty was marked busy.
1269 */
1270 if (((scif_fdr_read() & SCFDR2_TXCNT) >> 8) != 16) { /* XXX (msaitoh) */
1271 /*
1272 * If we've delayed a parameter change, do it now, and restart
1273 * output.
1274 */
1275 if (sc->sc_heldchange) {
1276 sc->sc_heldchange = 0;
1277 sc->sc_tbc = sc->sc_heldtbc;
1278 sc->sc_heldtbc = 0;
1279 }
1280
1281 /* Output the next chunk of the contiguous buffer, if any. */
1282 if (sc->sc_tbc > 0) {
1283 int n;
1284 int maxchars;
1285 int i;
1286
1287 n = sc->sc_tbc;
1288 maxchars = sc->sc_fifolen -
1289 ((scif_fdr_read() & SCFDR2_TXCNT) >> 8);
1290 if (n > maxchars)
1291 n = maxchars;
1292
1293 for (i = 0; i < n; i++) {
1294 scif_putc(*(sc->sc_tba));
1295 sc->sc_tba++;
1296 }
1297 sc->sc_tbc -= n;
1298 } else {
1299 /* Disable transmit completion interrupts if necessary. */
1300 #if 0
1301 if (ISSET(sc->sc_ier, IER_ETXRDY))
1302 #endif
1303 scif_scr_write(scif_scr_read() & ~SCSCR2_TIE);
1304
1305 if (sc->sc_tx_busy) {
1306 sc->sc_tx_busy = 0;
1307 sc->sc_tx_done = 1;
1308 }
1309 }
1310 }
1311
1312 /* Wake up the poller. */
1313 softintr_schedule(sc->sc_si);
1314
1315 return (1);
1316 }
1317
1318 void
scifcnprobe(struct consdev * cp)1319 scifcnprobe(struct consdev *cp)
1320 {
1321 int maj;
1322
1323 /* locate the major number */
1324 for (maj = 0; maj < nchrdev; maj++)
1325 if (cdevsw[maj].d_open == scifopen)
1326 break;
1327
1328 cp->cn_dev = makedev(maj, 0);
1329 #ifdef SCIFCONSOLE
1330 cp->cn_pri = CN_HIGHPRI;
1331 #else
1332 cp->cn_pri = CN_LOWPRI;
1333 #endif
1334 }
1335
1336 void
scifcninit(struct consdev * cp)1337 scifcninit(struct consdev *cp)
1338 {
1339 InitializeScif(scifcn_speed);
1340 scifisconsole = 1;
1341 }
1342
1343 int
scifcngetc(dev_t dev)1344 scifcngetc(dev_t dev)
1345 {
1346 int c;
1347 int s;
1348
1349 s = spltty();
1350 c = scif_getc();
1351 splx(s);
1352
1353 return (c);
1354 }
1355
1356 void
scifcnputc(dev_t dev,int c)1357 scifcnputc(dev_t dev, int c)
1358 {
1359 int s;
1360
1361 s = spltty();
1362 scif_putc((u_char)c);
1363 splx(s);
1364 }
1365