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Searched refs:sclk_mask (Results 1 – 5 of 5) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/pm/swsmu/smu12/
H A Drenoir_ppt.c252 uint32_t *sclk_mask, in renoir_get_profiling_clk_mask() argument
258 if (sclk_mask) in renoir_get_profiling_clk_mask()
259 *sclk_mask = 0; in renoir_get_profiling_clk_mask()
265 if (sclk_mask) in renoir_get_profiling_clk_mask()
267 *sclk_mask = 3 - 1; in renoir_get_profiling_clk_mask()
935 uint32_t sclk_mask, mclk_mask, soc_mask; in renoir_set_performance_level() local
1016 &sclk_mask, in renoir_set_performance_level()
1021 renoir_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask); in renoir_set_performance_level()
/openbsd/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/
H A Dvega12_hwmgr.c1718 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega12_get_profiling_clk_mask() argument
1725 *sclk_mask = 0; in vega12_get_profiling_clk_mask()
1732 *sclk_mask = VEGA12_UMD_PSTATE_GFXCLK_LEVEL; in vega12_get_profiling_clk_mask()
1738 *sclk_mask = 0; in vega12_get_profiling_clk_mask()
1742 *sclk_mask = gfx_dpm_table->count - 1; in vega12_get_profiling_clk_mask()
1772 uint32_t sclk_mask = 0; in vega12_dpm_force_dpm_level() local
1790 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega12_dpm_force_dpm_level()
1793 vega12_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask); in vega12_dpm_force_dpm_level()
H A Dvega20_hwmgr.c2523 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega20_get_profiling_clk_mask() argument
2530 *sclk_mask = 0; in vega20_get_profiling_clk_mask()
2537 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL; in vega20_get_profiling_clk_mask()
2543 *sclk_mask = 0; in vega20_get_profiling_clk_mask()
2547 *sclk_mask = gfx_dpm_table->count - 1; in vega20_get_profiling_clk_mask()
2723 uint32_t sclk_mask, mclk_mask, soc_mask; in vega20_dpm_force_dpm_level() local
2742 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega20_dpm_force_dpm_level()
2745 vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask); in vega20_dpm_force_dpm_level()
H A Dsmu7_hwmgr.c3170 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask) in smu7_get_profiling_clk() argument
3200 *sclk_mask = count; in smu7_get_profiling_clk()
3205 *sclk_mask = 0; in smu7_get_profiling_clk()
3208 *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; in smu7_get_profiling_clk()
3215 *sclk_mask = count; in smu7_get_profiling_clk()
3220 *sclk_mask = 0; in smu7_get_profiling_clk()
3223 *sclk_mask = table_info->vdd_dep_on_sclk->count - 1; in smu7_get_profiling_clk()
3240 uint32_t sclk_mask = 0; in smu7_force_dpm_level() local
3258 ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask); in smu7_force_dpm_level()
3261 smu7_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask); in smu7_force_dpm_level()
H A Dvega10_hwmgr.c4183 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega10_get_profiling_clk_mask() argument
4191 *sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL; in vega10_get_profiling_clk_mask()
4197 *sclk_mask = 0; in vega10_get_profiling_clk_mask()
4205 *sclk_mask = 4; in vega10_get_profiling_clk_mask()
4207 *sclk_mask = table_info->vdd_dep_on_sclk->count - 1; in vega10_get_profiling_clk_mask()
4300 uint32_t sclk_mask = 0; in vega10_dpm_force_dpm_level() local
4318 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega10_dpm_force_dpm_level()
4321 vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask); in vega10_dpm_force_dpm_level()