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Searched refs:sdma_offsets (Results 1 – 4 of 4) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dsdma_v3_0.c74 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = variable
578 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); in sdma_v3_0_ctx_switch_enable()
585 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], in sdma_v3_0_ctx_switch_enable()
587 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], in sdma_v3_0_ctx_switch_enable()
597 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); in sdma_v3_0_ctx_switch_enable()
660 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], in sdma_v3_0_gfx_resume()
678 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); in sdma_v3_0_gfx_resume()
680 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); in sdma_v3_0_gfx_resume()
681 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); in sdma_v3_0_gfx_resume()
715 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); in sdma_v3_0_gfx_resume()
[all …]
H A Damdgpu_cik_sdma.c47 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = variable
193 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], in cik_sdma_ring_set_wptr()
317 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0); in cik_sdma_gfx_stop()
371 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); in cik_ctx_switch_enable()
386 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); in cik_ctx_switch_enable()
447 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], in cik_sdma_gfx_resume()
463 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); in cik_sdma_gfx_resume()
464 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); in cik_sdma_gfx_resume()
465 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); in cik_sdma_gfx_resume()
483 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], in cik_sdma_gfx_resume()
[all …]
H A Dsdma_v2_4.c60 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = variable
385 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); in sdma_v2_4_enable()
390 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); in sdma_v2_4_enable()
417 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); in sdma_v2_4_gfx_resume()
422 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], in sdma_v2_4_gfx_resume()
439 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); in sdma_v2_4_gfx_resume()
440 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); in sdma_v2_4_gfx_resume()
441 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); in sdma_v2_4_gfx_resume()
442 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); in sdma_v2_4_gfx_resume()
445 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], in sdma_v2_4_gfx_resume()
[all …]
H A Damdgpu_si_dma.c30 const u32 sdma_offsets[SDMA_MAX_INSTANCE] = variable
122 rb_cntl = RREG32(DMA_RB_CNTL + sdma_offsets[i]); in si_dma_stop()
124 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_stop()
139 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); in si_dma_start()
147 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_start()
150 WREG32(DMA_RB_RPTR + sdma_offsets[i], 0); in si_dma_start()
151 WREG32(DMA_RB_WPTR + sdma_offsets[i], 0); in si_dma_start()
167 WREG32(DMA_IB_CNTL + sdma_offsets[i], ib_cntl); in si_dma_start()
169 dma_cntl = RREG32(DMA_CNTL + sdma_offsets[i]); in si_dma_start()
171 WREG32(DMA_CNTL + sdma_offsets[i], dma_cntl); in si_dma_start()
[all …]