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Searched refs:simulated (Results 1 – 22 of 22) sorted by relevance

/openbsd/sys/dev/pci/drm/i915/
H A Di915_gpu_error.h64 bool simulated; member
143 bool simulated; member
205 bool simulated; member
H A Di915_gpu_error.c1446 bool simulated; in record_context() local
1475 simulated = i915_gem_context_no_error_capture(ctx); in record_context()
1478 return simulated; in record_context()
1615 ee->simulated |= record_context(&ee->context, ce); in engine_coredump_add_context()
1616 if (ee->simulated) in engine_coredump_add_context()
1757 gt->simulated |= ee->simulated; in gt_record_engines()
1758 if (ee->simulated) { in gt_record_engines()
2194 error->simulated |= error->gt->simulated; in __i915_gpu_coredump()
2230 if (error->simulated || in i915_error_state_store()
/openbsd/gnu/usr.bin/binutils/include/mpw/
H A DChangeLog57 * utime.h, varargs.h: New files, simulated Posix.
59 simulated Posix.
/openbsd/gnu/llvm/llvm/docs/CommandGuide/
H A Dllvm-mca.rst204 view because it doesn't require that the code is simulated. It instead prints
487 for a total of 900 simulated instructions. The total number of simulated micro
497 to the out-of-order backend every simulated cycle. For processors with an
499 to the backend every simulated cycle.
506 (i.e. iterations) that can be executed per simulated clock cycle in the absence
514 Field 'uOps Per Cycle' is computed dividing the total number of simulated micro
752 48.07% of the simulated run. Almost all those pressure increase events were
850 this case, of the 610 simulated cycles, single opcodes were issued 306 times
923 simulated hardware schedulers.
925 The size of a dispatch group depends on the availability of the simulated
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/openbsd/gnu/llvm/llvm/docs/
H A DJITLink.rst262 definitions within the same simulated dylib (e.g. ORC ``JITDylib``) or
658 model requires that all code and data for a simulated dylib is allocated within
675 This method takes a ``JITLinkDylib*`` representing the target simulated
678 argument to manage a per-simulated-dylib memory pool (since code model
1118 treat every object as a separate simulated dylib for the purposes of
1122 range pool for each simulated dylib guarantees that the relaxation
/openbsd/sys/dev/pci/drm/i915/gt/
H A Dintel_execlists_submission.c2244 gt->simulated = gt->engine->simulated; in execlists_capture_work()
2245 cap->error->simulated = gt->simulated; in execlists_capture_work()
/openbsd/usr.bin/file/magdir/
H A Dmacintosh129 #>65 string CIRC (simulated circuit)
/openbsd/gnu/usr.bin/gcc/gcc/
H A Dgcc.hlp394 under VAX-C. This can be easily simulated, however, by globaldefing
H A DFSFChangeLog.109484 don't move floating point to memory if it is being simulated with
/openbsd/gnu/llvm/clang/docs/analyzer/developer-docs/
H A DIPA.rst221 information is constrained enough for a simulated C++/Objective-C object that
/openbsd/gnu/usr.bin/perl/pod/
H A Dperlreguts.pod772 simulated recursion.
H A Dperlrun.pod117 Unix's C<#!> technique can be simulated on other systems:
/openbsd/gnu/usr.bin/perl/cpan/perlfaq/lib/
H A Dperlfaq3.pod411 OptiPerl is a Windows IDE with simulated CGI environment, including
/openbsd/gnu/usr.bin/gcc/gcc/doc/
H A Dtm.texi5535 constraint to issue insns on the same simulated processor cycle (see
5643 when the new simulated processor cycle starts. Usage of the hook may
5647 when the new simulated processor cycle starts.
5657 simulated processor cycle finishes.
H A Dmd.texi5371 on a given simulated processor cycle. The pipeline hazard recognizer is
/openbsd/gnu/gcc/gcc/doc/
H A Dtm.texi5848 constraint to issue insns on the same simulated processor cycle (see
5965 when the new simulated processor cycle starts. Usage of the hook may
5969 when the new simulated processor cycle starts.
5979 simulated processor cycle finishes.
H A Dgccint.info18133 a given simulated processor cycle. The pipeline hazard recognizer is
24257 additional constraint to issue insns on the same simulated
24375 when the new simulated processor cycle starts. Usage of the hook
24379 change the state when the new simulated processor cycle starts.
24387 simulated processor cycle finishes.
H A Dmd.texi6704 on a given simulated processor cycle. The pipeline hazard recognizer is
/openbsd/gnu/usr.bin/binutils/gdb/
H A DChangeLog-19992817 interrupting a simulated synchronous execution command.
5595 and target is async, start the target in simulated synchronous
/openbsd/gnu/usr.bin/binutils-2.17/cpu/
H A Dfrv.cpu6929 (nop) ; not simulated
6942 (nop) ; not simulated
/openbsd/gnu/usr.bin/binutils/gdb/doc/
H A Dgdb.texinfo13226 Debug programs on a simulated CPU. If the simulator supports setup
13231 After specifying this target, you can debug programs for the simulated
13256 simulated clock ticks.
/openbsd/gnu/usr.bin/binutils/gdb/testsuite/
H A DChangeLog8146 don't currently support passing such an arg into the simulated