Home
last modified time | relevance | path

Searched refs:total_dcn_read_bw_with_flip (Results 1 – 8 of 8) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_mode_vba_20.c2238 double total_dcn_read_bw_with_flip = 0; in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation() local
2299 total_dcn_read_bw_with_flip = in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2300 total_dcn_read_bw_with_flip in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2313 if (total_dcn_read_bw_with_flip > mode_lib->vba.ReturnBW) { in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4900 mode_lib->vba.total_dcn_read_bw_with_flip = 0.0; in dml20_ModeSupportAndSystemConfigurationFull()
4902 mode_lib->vba.total_dcn_read_bw_with_flip = in dml20_ModeSupportAndSystemConfigurationFull()
4903 mode_lib->vba.total_dcn_read_bw_with_flip in dml20_ModeSupportAndSystemConfigurationFull()
4914 if (mode_lib->vba.total_dcn_read_bw_with_flip in dml20_ModeSupportAndSystemConfigurationFull()
H A Ddisplay_mode_vba_20v2.c2272 double total_dcn_read_bw_with_flip = 0; in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation() local
2333 total_dcn_read_bw_with_flip = in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2334 total_dcn_read_bw_with_flip in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2347 if (total_dcn_read_bw_with_flip > mode_lib->vba.ReturnBW) { in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
5019 mode_lib->vba.total_dcn_read_bw_with_flip = 0.0; in dml20v2_ModeSupportAndSystemConfigurationFull()
5021 mode_lib->vba.total_dcn_read_bw_with_flip = in dml20v2_ModeSupportAndSystemConfigurationFull()
5022 mode_lib->vba.total_dcn_read_bw_with_flip in dml20v2_ModeSupportAndSystemConfigurationFull()
5033 if (mode_lib->vba.total_dcn_read_bw_with_flip in dml20v2_ModeSupportAndSystemConfigurationFull()
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_mode_vba_30.c2690 v->total_dcn_read_bw_with_flip = 0.0; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2693 v->total_dcn_read_bw_with_flip = v->total_dcn_read_bw_with_flip + dml_max3( in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2713 if (v->total_dcn_read_bw_with_flip > v->ReturnBW) { in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2715 v->total_dcn_read_bw_with_flip = MaxTotalRDBandwidth; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4978 v->total_dcn_read_bw_with_flip = 0.0; in dml30_ModeSupportAndSystemConfigurationFull()
4980 v->total_dcn_read_bw_with_flip = v->total_dcn_read_bw_with_flip in dml30_ModeSupportAndSystemConfigurationFull()
4994 if (v->total_dcn_read_bw_with_flip > v->ReturnBWPerState[i][j]) { in dml30_ModeSupportAndSystemConfigurationFull()
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn31/
H A Ddisplay_mode_vba_31.c2865 v->total_dcn_read_bw_with_flip = 0.0;
2868 v->total_dcn_read_bw_with_flip = v->total_dcn_read_bw_with_flip
2892 if (v->total_dcn_read_bw_with_flip > v->ReturnBW) {
2894 …otal_dcn_read_bw_with_flip %f (bw w/ flip too high!)\n", __func__, v->total_dcn_read_bw_with_flip);
2897 v->total_dcn_read_bw_with_flip = MaxTotalRDBandwidth;
5304 v->total_dcn_read_bw_with_flip = 0.0;
5306 v->total_dcn_read_bw_with_flip = v->total_dcn_read_bw_with_flip
5320 if (v->total_dcn_read_bw_with_flip > v->ReturnBWPerState[i][j]) {
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn314/
H A Ddisplay_mode_vba_314.c2886 v->total_dcn_read_bw_with_flip = 0.0;
2889 v->total_dcn_read_bw_with_flip = v->total_dcn_read_bw_with_flip
2913 if (v->total_dcn_read_bw_with_flip > v->ReturnBW) {
2915 …otal_dcn_read_bw_with_flip %f (bw w/ flip too high!)\n", __func__, v->total_dcn_read_bw_with_flip);
2918 v->total_dcn_read_bw_with_flip = MaxTotalRDBandwidth;
5391 v->total_dcn_read_bw_with_flip = 0.0;
5393 v->total_dcn_read_bw_with_flip = v->total_dcn_read_bw_with_flip
5407 if (v->total_dcn_read_bw_with_flip > v->ReturnBWPerState[i][j]) {
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_mode_vba_21.c2367 mode_lib->vba.total_dcn_read_bw_with_flip = 0.0; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2370 mode_lib->vba.total_dcn_read_bw_with_flip = in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2371 mode_lib->vba.total_dcn_read_bw_with_flip + dml_max3( in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2388 if (mode_lib->vba.total_dcn_read_bw_with_flip > mode_lib->vba.ReturnBW) { in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4958 mode_lib->vba.total_dcn_read_bw_with_flip = 0.0; in dml21_ModeSupportAndSystemConfigurationFull()
4960 … mode_lib->vba.total_dcn_read_bw_with_flip = mode_lib->vba.total_dcn_read_bw_with_flip + dml_max3( in dml21_ModeSupportAndSystemConfigurationFull()
4971 if (mode_lib->vba.total_dcn_read_bw_with_flip in dml21_ModeSupportAndSystemConfigurationFull()
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/
H A Ddisplay_mode_vba.h734 double total_dcn_read_bw_with_flip; member
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_mode_vba_32.c1093 &v->total_dcn_read_bw_with_flip, // Single *TotalBandwidth in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()