1 /* $OpenBSD: if_urlreg.h,v 1.15 2013/10/28 16:08:08 mpi Exp $ */ 2 /* $NetBSD: if_urlreg.h,v 1.1 2002/03/28 21:09:11 ichiro Exp $ */ 3 /* 4 * Copyright (c) 2001, 2002 5 * Shingo WATANABE <nabe@nabechan.org>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the author nor the names of any co-contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 #define URL_IFACE_INDEX 0 34 #define URL_CONFIG_NO 1 35 36 #define URL_TX_LIST_CNT 1 37 #define URL_RX_LIST_CNT 1 38 39 #define URL_TX_TIMEOUT 1000 40 #define URL_TIMEOUT 10000 41 42 /* Packet length */ 43 #define URL_MAX_MTU 1536 44 #define URL_MIN_FRAME_LEN 60 45 #define URL_BUFSZ URL_MAX_MTU 46 47 /* Request */ 48 #define URL_REQ_MEM 0x05 49 50 #define URL_CMD_READMEM 1 51 #define URL_CMD_WRITEMEM 2 52 53 /* Registers */ 54 #define URL_IDR0 0x0120 /* Ethernet Address, load from 93C46 */ 55 #define URL_IDR1 0x0121 /* Ethernet Address, load from 93C46 */ 56 #define URL_IDR2 0x0122 /* Ethernet Address, load from 93C46 */ 57 #define URL_IDR3 0x0123 /* Ethernet Address, load from 93C46 */ 58 #define URL_IDR4 0x0124 /* Ethernet Address, load from 93C46 */ 59 #define URL_IDR5 0x0125 /* Ethernet Address, load from 93C46 */ 60 61 #define URL_MAR0 0x0126 /* Multicast register */ 62 #define URL_MAR1 0x0127 /* Multicast register */ 63 #define URL_MAR2 0x0128 /* Multicast register */ 64 #define URL_MAR3 0x0129 /* Multicast register */ 65 #define URL_MAR4 0x012a /* Multicast register */ 66 #define URL_MAR5 0x012b /* Multicast register */ 67 #define URL_MAR6 0x012c /* Multicast register */ 68 #define URL_MAR7 0x012d /* Multicast register */ 69 #define URL_MAR URL_MAR0 70 71 #define URL_CR 0x012e /* Command Register */ 72 #define URL_CR_WEPROM (1<<5) /* EEPROM Write Enable */ 73 #define URL_CR_SOFT_RST (1<<4) /* Software Reset */ 74 #define URL_CR_RE (1<<3) /* Ethernet Receive Enable */ 75 #define URL_CR_TE (1<<2) /* Ethernet Transmit Enable */ 76 #define URL_CR_EP3CLREN (1<<1) /* Enable clearing the performance counter */ 77 #define URL_CR_AUTOLOAD (1<<0) /* Auto-load the contents of 93C46 */ 78 79 #define URL_TCR 0x012f /* Transmit Control Register */ 80 #define URL_TCR_TXRR1 (1<<7) /* TX Retry Count */ 81 #define URL_TCR_TXRR0 (1<<6) /* TX Retry Count */ 82 #define URL_TCR_IFG1 (1<<4) /* Interframe Gap Time */ 83 #define URL_TCR_IFG0 (1<<3) /* Interframe Gap Time */ 84 #define URL_TCR_NOCRC (1<<0) /* no CRC Append */ 85 86 #define URL_RCR 0x0130 /* Receive Configuration Register */ 87 #define URL_RCR_TAIL (1<<7) 88 #define URL_RCR_AER (1<<6) 89 #define URL_RCR_AR (1<<5) 90 #define URL_RCR_AM (1<<4) 91 #define URL_RCR_AB (1<<3) 92 #define URL_RCR_AD (1<<2) 93 #define URL_RCR_AAM (1<<1) 94 #define URL_RCR_AAP (1<<0) 95 96 #define URL_MSR 0x137 /* Media Status Register */ 97 #define URL_MSR_TXFCE (1<<7) 98 #define URL_MSR_RXFCE (1<<6) 99 #define URL_MSR_DUPLEX (1<<4) 100 #define URL_MSR_SPEED_100 (1<<3) 101 #define URL_MSR_LINK (1<<2) 102 #define URL_MSR_TXPF (1<<1) 103 #define URL_MSR_RXPF (1<<0) 104 105 #define URL_PHYADD 0x138 /* MII PHY Address select */ 106 #define URL_PHYADD_MASK 0x1f /* MII PHY Address select */ 107 108 #define URL_PHYDAT 0x139 /* MII PHY data */ 109 110 #define URL_PHYCNT 0x13b /* MII PHY control */ 111 #define URL_PHYCNT_PHYOWN (1<<6) /* Own bit */ 112 #define URL_PHYCNT_RWCR (1<<5) /* MII management data R/W control */ 113 #define URL_PHY_PHYOFF_MASK 0x1f /* PHY register offset */ 114 115 #define URL_BMCR 0x140 /* Basic mode control register */ 116 #define URL_BMSR 0x142 /* Basic mode status register */ 117 #define URL_ANAR 0x144 /* Auto-negotiation advertisement register */ 118 #define URL_ANLP 0x146 /* Auto-negotiation link partner ability register */ 119 120 121 typedef uWord url_rxhdr_t; /* Receive Header */ 122 #define URL_RXHDR_BYTEC_MASK (0x0fff) /* RX bytes count */ 123 #define URL_RXHDR_VALID_MASK (0x1000) /* Valid packet */ 124 #define URL_RXHDR_RUNTPKT_MASK (0x2000) /* Runt packet */ 125 #define URL_RXHDR_PHYPKT_MASK (0x4000) /* Physical match packet */ 126 #define URL_RXHDR_MCASTPKT_MASK (0x8000) /* Multicast packet */ 127 128 #define GET_IFP(sc) (&(sc)->sc_ac.ac_if) 129 #define GET_MII(sc) (&(sc)->sc_mii) 130 131 struct url_chain { 132 struct url_softc *url_sc; 133 struct usbd_xfer *url_xfer; 134 char *url_buf; 135 struct mbuf *url_mbuf; 136 int url_idx; 137 }; 138 139 struct url_cdata { 140 struct url_chain url_tx_chain[URL_TX_LIST_CNT]; 141 struct url_chain url_rx_chain[URL_TX_LIST_CNT]; 142 #if 0 143 /* XXX: Interrupt Endpoint is not yet supported! */ 144 struct url_intrpkg url_ibuf; 145 #endif 146 int url_tx_prod; 147 int url_tx_cons; 148 int url_tx_cnt; 149 int url_rx_prod; 150 }; 151 152 struct url_softc { 153 struct device sc_dev; /* base device */ 154 struct usbd_device *sc_udev; 155 156 /* USB */ 157 struct usbd_interface *sc_ctl_iface; 158 /* int sc_ctl_iface_no; */ 159 int sc_bulkin_no; /* bulk in endpoint */ 160 int sc_bulkout_no; /* bulk out endpoint */ 161 int sc_intrin_no; /* intr in endpoint */ 162 struct usbd_pipe *sc_pipe_rx; 163 struct usbd_pipe *sc_pipe_tx; 164 struct usbd_pipe *sc_pipe_intr; 165 struct timeout sc_stat_ch; 166 u_int sc_rx_errs; 167 /* u_int sc_intr_errs; */ 168 struct timeval sc_rx_notice; 169 170 /* Ethernet */ 171 struct arpcom sc_ac; /* ethernet common */ 172 struct mii_data sc_mii; 173 struct rwlock sc_mii_lock; 174 int sc_link; 175 #define sc_media url_mii.mii_media 176 struct url_cdata sc_cdata; 177 178 int sc_refcnt; 179 180 struct usb_task sc_tick_task; 181 struct usb_task sc_stop_task; 182 183 u_int16_t sc_flags; 184 }; 185