| /openbsd/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86CallingConv.td | 88 // Promote i1/i8/i16/v1i1 arguments to i32.
162 // Promote i1, v1i1, v8i1 arguments to i8.
223 CCIfType<[v1i1], CCPromoteToType<i8>>,
405 CCIfType<[v1i1], CCPromoteToType<i8>>,
520 // Promote i1/i8/i16/v1i1 arguments to i32.
630 // Promote i1/v1i1 arguments to i8.
631 CCIfType<[i1, v1i1], CCPromoteToType<i8>>,
893 // Promote i1/i8/i16/v1i1 arguments to i32.
917 // Promote i1/i8/i16/v1i1 arguments to i32.
961 // Promote i1/i8/i16/v1i1 arguments to i32.
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| H A D | X86InstrVecCompiler.td | 183 def maskzeroupperv1i1 : maskzeroupper<v1i1, VK1>;
270 (v1i1 VK1:$mask), (iPTR 0))),
298 (v1i1 VK1:$mask), (iPTR 0))),
348 (v1i1 VK1:$mask), (iPTR 0))),
361 (v1i1 VK1:$mask), (iPTR 0))),
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| H A D | X86RegisterInfo.td | 610 def VK1 : RegisterClass<"X86", [v1i1], 16, (sequence "K%u", 0, 7)> {let Size = 16;}
628 def VK1WM : RegisterClass<"X86", [v1i1], 16, (sub VK1, K0)> {let Size = 16;}
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| H A D | X86InstrFragmentsSIMD.td | 299 SDTypeProfile<1, 3, [SDTCisVT<1, v1i1>,
496 SDTypeProfile<1, 2, [SDTCisVT<0, v1i1>,
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| H A D | X86InstrAVX512.td | 183 def v1i1_info : X86KVectorVTInfo<VK1, VK1WM, v1i1>;
2948 def : Pat<(v1i1 (load addr:$src)),
2983 defm : operation_gpr_mask_copy_lowering<VK1, v1i1>;
3374 def : Pat<(v1i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK1)>;
3378 def : Pat<(v1i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK1)>;
3390 defm : operation_subvector_mask_lowering<VK1, v1i1, VK2, v2i1>;
3391 defm : operation_subvector_mask_lowering<VK1, v1i1, VK4, v4i1>;
3392 defm : operation_subvector_mask_lowering<VK1, v1i1, VK8, v8i1>;
3393 defm : operation_subvector_mask_lowering<VK1, v1i1, VK16, v16i1>;
3394 defm : operation_subvector_mask_lowering<VK1, v1i1, VK32, v32i1>;
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| H A D | X86ISelLowering.cpp | 1586 addRegisterClass(MVT::v1i1, &X86::VK1RegClass); in X86TargetLowering()
1592 setOperationAction(ISD::SELECT, MVT::v1i1, Custom); in X86TargetLowering()
1593 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v1i1, Custom); in X86TargetLowering()
1594 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i1, Custom); in X86TargetLowering()
1611 setOperationAction(ISD::LOAD, MVT::v1i1, Custom); in X86TargetLowering()
1616 setOperationAction(ISD::STORE, MVT::v1i1, Custom); in X86TargetLowering()
1647 for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1 }) in X86TargetLowering()
3108 if (ValVT == MVT::v1i1) in lowerMasksToReg()
3483 if (ValVT == MVT::v1i1) in lowerRegToMasks()
4182 else if (RegVT == MVT::v1i1) in LowerFormalArguments()
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| H A D | X86InstrCompiler.td | 613 defm _VK1 : CMOVrr_PSEUDO<VK1, v1i1>;
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| /openbsd/gnu/llvm/llvm/include/llvm/Support/ |
| H A D | MachineValueType.h | 66 v1i1 = 17, // 1 x i1 enumerator
143 FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i1,
203 FIRST_FIXEDLEN_VECTOR_VALUETYPE = v1i1,
277 FIRST_VECTOR_VALUETYPE = v1i1,
547 case v1i1: in getVectorElementType()
880 case v1i1: in getVectorMinNumElements()
939 case v1i1: return TypeSize::Fixed(1); in getSizeInBits()
1269 if (NumElements == 1) return MVT::v1i1; in getVectorVT()
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| /openbsd/gnu/llvm/llvm/include/llvm/CodeGen/ |
| H A D | ValueTypes.td | 39 def v1i1 : ValueType<1, 17>; // 1 x i1 vector value
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| /openbsd/gnu/llvm/llvm/utils/TableGen/ |
| H A D | CodeGenTarget.cpp | 83 case MVT::v1i1: return "MVT::v1i1"; in getEnumName()
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| /openbsd/gnu/llvm/llvm/lib/CodeGen/ |
| H A D | ValueTypes.cpp | 213 case MVT::v1i1: in getTypeForEVT()
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| /openbsd/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 802 assert(N->getValueType(0) == MVT::v1i1 && "Expected v1i1 type"); in ScalarizeVecOp_VSETCC()
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| /openbsd/gnu/llvm/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 10624 if ((SrcVT == MVT::v1i1 || SrcVT == MVT::v2i1 || SrcVT == MVT::v4i1) && in PerformDAGCombine()
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