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Searched refs:v32i32 (Results 1 – 22 of 22) sorted by relevance

/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonCallingConv.td118 CCIfType<[v32i32,v64i16,v128i8],
124 CCIfType<[v32i32,v64i16,v128i8],
129 CCIfType<[v32i32,v64i16,v128i8,v32f32,v64f16],
135 CCIfType<[v32i32,v64i16,v128i8,v32f32,v64f16],
150 CCIfType<[v32i32,v64i16,v128i8],
155 CCIfType<[v32i32,v64i16,v128i8,v32f32,v64f16],
H A DHexagonIntrinsicsV60.td15 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))),
16 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_lo)) >;
18 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))),
19 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_hi)) >;
21 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))),
24 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))),
46 def : Pat <(v128i1 (bitconvert (v32i32 HvxVR:$src1))),
55 def : Pat <(v32i32 (bitconvert (v128i1 HvxQR:$src1))),
76 (v32i32 (V6_vandqrt (v128i1 HvxQR:$src1),
637 (v32i32 (V6_hi HvxWR:$Vdd)),
[all …]
H A DHexagonIntrinsics.td265 def : Pat <(v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))),
266 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_lo))>,
269 def : Pat <(v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))),
270 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_hi))>,
273 def : Pat <(v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))),
274 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_lo))>,
277 def : Pat <(v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))),
278 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_hi))>,
284 (v32i32 (V6_hi HvxWR:$Vdd)),
285 (v32i32 (V6_lo HvxWR:$Vdd))))>,
H A DHexagonRegisterInfo.td481 [v16i32, v32i32, v16i32]>;
492 [v32i32, v64i32, v32i32]>;
H A DHexagonISelLoweringHVX.cpp35 static const MVT LegalW64[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 };
36 static const MVT LegalV128[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 };
63 addRegisterClass(MVT::v32i32, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
78 addRegisterClass(MVT::v32i32, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
99 MVT WordV = Use64b ? MVT::v16i32 : MVT::v32i32; in initializeHVXLowering()
402 for (MVT T: {MVT::v64i8, MVT::v64i16, MVT::v32i8, MVT::v32i16, MVT::v32i32}) in initializeHVXLowering()
H A DHexagonISelDAGToDAG.cpp118 case MVT::v32i32: in INITIALIZE_PASS()
508 case MVT::v32i32: in SelectIndexedStore()
H A DHexagonISelDAGToDAGHVX.cpp2949 SDVTList VTs = CurDAG->getVTList(MVT::v32i32, MVT::v128i1); in SelectHVXDualOutput()
2963 SDVTList VTs = CurDAG->getVTList(MVT::v32i32, MVT::v128i1); in SelectHVXDualOutput()
H A DHexagonPatternsHVX.td572 // Pattern for (v32i8 (trunc v32i32:$Vs)) after widening:
H A DHexagonInstrInfo.cpp2734 case MVT::v32i32: in isValidAutoIncImm()
/openbsd/gnu/llvm/llvm/include/llvm/Support/
H A DMachineValueType.h122 v32i32 = 68, // 32 x i32 enumerator
458 SimpleTy == MVT::v64i16 || SimpleTy == MVT::v32i32 || in is1024BitVector()
618 case v32i32: in getVectorElementType()
775 case v32i32: in getVectorMinNumElements()
1086 case v32i32: in getSizeInBits()
1330 if (NumElements == 32) return MVT::v32i32; in getVectorVT()
/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIInstructions.td1408 i32, v32i32, Index, !cast<SubRegIndex>(sub#Index)
1412 i32, v32i32, Index, !cast<SubRegIndex>(sub#Index)
1625 def : BitConvert <v32i32, v32f32, VReg_1024>;
1626 def : BitConvert <v32f32, v32i32, VReg_1024>;
1629 def : BitConvert <v16i64, v32i32, VReg_1024>;
1630 def : BitConvert <v32i32, v16i64, VReg_1024>;
1634 def : BitConvert <v32i32, v16f64, VReg_1024>;
1635 def : BitConvert <v16f64, v32i32, VReg_1024>;
2165 defm : SI_INDIRECT_Pattern <v32i32, i32, "V32">;
H A DSIRegisterInfo.td901 defm "" : SRegClass<32, [v32i32, v32f32, v16i64, v16f64], SGPR_1024Regs>;
954 defm VReg_1024 : VRegClass<32, [v32i32, v32f32, v16i64, v16f64], (add VGPR_1024)>;
987 defm AReg_1024 : ARegClass<32, [v32i32, v32f32, v16i64, v16f64], (add AGPR_1024)>;
H A DAMDGPUISelLowering.cpp103 AddPromotedToType(ISD::LOAD, MVT::v32f32, MVT::v32i32); in AMDGPUTargetLowering()
136 AddPromotedToType(ISD::LOAD, MVT::v16i64, MVT::v32i32); in AMDGPUTargetLowering()
139 AddPromotedToType(ISD::LOAD, MVT::v16f64, MVT::v32i32); in AMDGPUTargetLowering()
229 AddPromotedToType(ISD::STORE, MVT::v32f32, MVT::v32i32); in AMDGPUTargetLowering()
262 AddPromotedToType(ISD::STORE, MVT::v16i64, MVT::v32i32); in AMDGPUTargetLowering()
265 AddPromotedToType(ISD::STORE, MVT::v16f64, MVT::v32i32); in AMDGPUTargetLowering()
372 MVT::v32f32, MVT::v32i32, MVT::v2f64, MVT::v2i64, MVT::v3f64, in AMDGPUTargetLowering()
H A DR600ISelLowering.cpp75 setTruncStoreAction(MVT::v32i32, MVT::v32i16, Custom); in R600TargetLowering()
80 setTruncStoreAction(MVT::v32i32, MVT::v32i8, Custom); in R600TargetLowering()
H A DSIISelLowering.cpp159 addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass); in SITargetLowering()
176 MVT::i1, MVT::v32i32}, in SITargetLowering()
183 MVT::i1, MVT::v32i32}, in SITargetLowering()
191 setTruncStoreAction(MVT::v32i32, MVT::v32i16, Expand); in SITargetLowering()
196 setTruncStoreAction(MVT::v32i32, MVT::v32i8, Expand); in SITargetLowering()
265 MVT::v32i32, MVT::v32f32}) { in SITargetLowering()
355 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v32i32); in SITargetLowering()
358 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v32i32); in SITargetLowering()
361 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v32i32); in SITargetLowering()
364 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v32i32); in SITargetLowering()
H A DSIInstrInfo.td2722 def VOP_V32I32_I32_I32_V32I32 : VOPProfile <[v32i32, i32, i32, v32i32]>;
/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/
H A DValueTypes.td95 def v32i32 : ValueType<1024, 68>; // 32 x i32 vector value
/openbsd/gnu/llvm/llvm/utils/TableGen/
H A DCodeGenTarget.cpp134 case MVT::v32i32: return "MVT::v32i32"; in getEnumName()
/openbsd/gnu/llvm/llvm/lib/CodeGen/
H A DValueTypes.cpp315 case MVT::v32i32: in getTypeForEVT()
/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp6416 {2, MVT::v32i32, 16}, // (load 64i32 and) deinterleave into 2 x 32i32 in getInterleavedMemoryOpCost()
6439 {3, MVT::v32i32, 32}, // (load 96i32 and) deinterleave into 3 x 32i32 in getInterleavedMemoryOpCost()
6462 {4, MVT::v32i32, 68}, // (load 128i32 and) deinterleave into 4 x 32i32 in getInterleavedMemoryOpCost()
6518 {2, MVT::v32i32, 16}, // interleave 2 x 32i32 into 64i32 (and store) in getInterleavedMemoryOpCost()
6542 {3, MVT::v32i32, 48}, // interleave 3 x 32i32 into 96i32 (and store) in getInterleavedMemoryOpCost()
6565 {4, MVT::v32i32, 64}, // interleave 4 x 32i32 into 128i32 (and store) in getInterleavedMemoryOpCost()
/openbsd/gnu/llvm/llvm/include/llvm/IR/
H A DIntrinsics.td310 def llvm_v32i32_ty : LLVMType<v32i32>; // 32 x i32
/openbsd/gnu/llvm/llvm/docs/
H A DLangRef.rst21846 …declare <32 x i1> @llvm.vp.icmp.v32i32(<32 x i32> <left_op>, <32 x i32> <right_op>, metadata <cond…