| /openbsd/gnu/llvm/llvm/include/llvm/Support/ |
| H A D | MachineValueType.h | 111 v3i32 = 57, // 3 x i32 enumerator
607 case v3i32: in getVectorElementType()
856 case v3i32: in getVectorMinNumElements()
1005 case v3i32: in getSizeInBits()
1319 if (NumElements == 3) return MVT::v3i32; in getVectorVT()
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| /openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | BUFInstructions.td | 821 "buffer_load_format_d16_xyz", v3i32
834 "buffer_store_format_d16_xyz", v3i32
889 "buffer_load_dwordx3", v3i32
926 defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_DWORDX3", v3i32, load_global>;
942 "buffer_store_dwordx3", v3i32, store_global
1269 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, v3i32, "BUFFER_LOAD_FORMAT_XYZ">;
1308 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, v3i32, "BUFFER_LOAD_DWORDX3">;
1357 defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, v3i32, "BUFFER_STORE_FORMAT_XYZ">;
1391 defm : MUBUF_StoreIntrinsicPat<SIbuffer_store, v3i32, "BUFFER_STORE_DWORDX3">;
1945 defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, v3i32, "TBUFFER_LOAD_FORMAT_XYZ">;
[all …]
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| H A D | FLATInstructions.td | 1128 def : FlatLoadPat <FLAT_LOAD_DWORDX3, load_flat, v3i32>;
1146 def : FlatStorePat <FLAT_STORE_DWORDX3, store_flat, v3i32>;
1383 defm : GlobalFLATLoadPats <GLOBAL_LOAD_DWORDX3, load_global, v3i32>;
1400 defm : GlobalFLATStorePats <GLOBAL_STORE_DWORDX3, store_global, v3i32>;
1541 defm : ScratchFLATLoadPats <SCRATCH_LOAD_DWORDX3, load_private, v3i32>;
1552 defm : ScratchFLATStorePats <SCRATCH_STORE_DWORDX3, store_private, v3i32>;
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| H A D | SIRegisterInfo.td | 888 defm "" : SRegClass<3, [v3i32, v3f32], SGPR_96Regs, TTMP_96Regs>;
940 defm VReg_96 : VRegClass<3, [v3i32, v3f32], (add VGPR_96)>;
974 defm AReg_96 : ARegClass<3, [v3i32, v3f32], (add AGPR_96)>;
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| H A D | AMDGPUISelLowering.cpp | 70 AddPromotedToType(ISD::LOAD, MVT::v3f32, MVT::v3i32); in AMDGPUTargetLowering()
196 AddPromotedToType(ISD::STORE, MVT::v3f32, MVT::v3i32); in AMDGPUTargetLowering()
293 setTruncStoreAction(MVT::v3i64, MVT::v3i32, Expand); in AMDGPUTargetLowering()
358 {MVT::v3i32, MVT::v3f32, MVT::v4i32, MVT::v4f32, in AMDGPUTargetLowering()
367 MVT::v2i32, MVT::v3f32, MVT::v3i32, MVT::v4f32, MVT::v4i32, in AMDGPUTargetLowering()
421 MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32, MVT::v6i32, MVT::v7i32, in AMDGPUTargetLowering()
465 AddPromotedToType(ISD::SELECT, MVT::v3f32, MVT::v3i32); in AMDGPUTargetLowering()
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| H A D | SIInstructions.td | 1171 i32, v3i32, Index, !cast<SubRegIndex>(sub#Index)
1174 i32, v3i32, Index, !cast<SubRegIndex>(sub#Index)
1487 def : BitConvert <v3i32, v3f32, SGPR_96>;
1488 def : BitConvert <v3f32, v3i32, SGPR_96>;
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| H A D | SIISelLowering.cpp | 96 addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass); in SITargetLowering()
173 {MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32, in SITargetLowering()
180 {MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32, in SITargetLowering()
187 setTruncStoreAction(MVT::v3i32, MVT::v3i16, Expand); in SITargetLowering()
204 setTruncStoreAction(MVT::v3i64, MVT::v3i32, Expand); in SITargetLowering()
226 {MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32, in SITargetLowering()
382 {MVT::v3i32, MVT::v3f32, MVT::v4i32, MVT::v4f32}, Custom); in SITargetLowering()
7815 Ops.push_back(DAG.getBuildVector(MVT::v3i32, DL, MergedLanes)); in LowerINTRINSIC_W_CHAIN()
7936 (VT == MVT::v3i32 || VT == MVT::v3f32)) { in getMemIntrinsicNode()
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| /openbsd/gnu/llvm/llvm/docs/GlobalISel/ |
| H A D | GMIR.rst | 186 ``<3 x s32>`` ``v3i32`` ``<3 x i32>``
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| /openbsd/gnu/llvm/llvm/include/llvm/CodeGen/ |
| H A D | ValueTypes.td | 84 def v3i32 : ValueType<96, 57>; // 3 x i32 vector value
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| /openbsd/gnu/llvm/llvm/utils/TableGen/ |
| H A D | CodeGenTarget.cpp | 123 case MVT::v3i32: return "MVT::v3i32"; in getEnumName()
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| /openbsd/gnu/llvm/llvm/lib/CodeGen/ |
| H A D | ValueTypes.cpp | 293 case MVT::v3i32: in getTypeForEVT()
|