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Searched refs:v4i8 (Results 1 – 25 of 42) sorted by relevance

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/openbsd/gnu/llvm/llvm/lib/Target/CSKY/
H A DCSKYCallingConv.td42 CCIfType<[v2i16, v4i8], CCAssignToReg<[R0, R1, R2, R3]>>,
43 CCIfType<[v2i16, v4i8], CCAssignToStack<4, 4>>,
55 CCIfType<[v2i16, v4i8], CCAssignToReg<[R0, R1]>>,
64 CCIfType<[v2i16, v4i8], CCAssignToReg<[R0, R1, R2, R3]>>,
65 CCIfType<[v2i16, v4i8], CCAssignToStack<4, 4>>,
77 CCIfType<[v2i16, v4i8], CCAssignToReg<[R0, R1]>>,
/openbsd/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsDSPInstrInfo.td1332 def : BitconvertPat<i32, v4i8, GPR32, DSPR>;
1334 def : BitconvertPat<v4i8, i32, DSPR, GPR32>;
1336 def : BitconvertPat<f32, v4i8, FGR32, DSPR>;
1338 def : BitconvertPat<v4i8, f32, DSPR, FGR32>;
1342 def : DSPPat<(v4i8 (load addr:$a)),
1346 def : DSPPat<(store (v4i8 DSPR:$val), addr:$a),
1360 def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
1361 def : DSPBinPat<ADDU_QB, v4i8, add>;
1362 def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
1363 def : DSPBinPat<SUBU_QB, v4i8, sub>;
[all …]
H A DMipsRegisterInfo.td318 def DSPR : GPR32Class<[v4i8, v2i16]>;
476 def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>;
H A DMipsSEISelLowering.cpp86 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8}; in MipsSETargetLowering()
868 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8)) in performSHLCombine()
925 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.hasDSPR2())) in performSRACombine()
937 if (((Ty != MVT::v2i16) || !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8)) in performSRLCombine()
964 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8)) in performSETCCCombine()
977 if (Ty == MVT::v2i16 || Ty == MVT::v4i8) { in performVSELECTCombine()
/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonCallingConv.td15 CCIfType<[i32,v2i16,v4i8],
39 CCIfType<[i32,v2i16,v4i8],
69 CCIfType<[i32,v2i16,v4i8],
97 CCIfType<[i32,v2i16,v4i8],
H A DHexagonPatterns.td83 def V4I8: PatLeaf<(v4i8 IntRegs:$R)>;
478 defm: NopCast_pat<i32, v4i8, IntRegs>;
479 defm: NopCast_pat<v2i16, v4i8, IntRegs>;
531 def: Pat<(v4i8 (azext V4I1:$Pu)),
551 def: Pat<(v4i8 (trunc V4I16:$Rs)),
576 def: Pat<(v4i8 (ssat V4I16:$Rs, v4i8)), (S2_vsathb V4I16:$Rs)>;
578 def: Pat<(v4i8 (usat V4I16:$Rs, v4i8)), (S2_vsathub V4I16:$Rs)>;
878 def: Pat<(select I1:$Pu, v4i8:$Rs, v4i8:$Rt),
879 (C2_mux I1:$Pu, v4i8:$Rs, v4i8:$Rt)>;
1822 // Multiplies two v4i8 vectors.
[all …]
H A DHexagonISelLowering.cpp1036 if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) { in LowerSETCC()
1094 if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) { in LowerVSELECT()
1471 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
1517 setOperationAction(ISD::SETCC, MVT::v4i8, Custom); in HexagonTargetLowering()
1679 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, MVT::v4i8, Legal); in HexagonTargetLowering()
1680 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, MVT::v4i8, Legal); in HexagonTargetLowering()
1681 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, MVT::v4i8, Legal); in HexagonTargetLowering()
1748 setOperationAction(ISD::VSELECT, MVT::v4i8, Custom); in HexagonTargetLowering()
1750 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8, Custom); in HexagonTargetLowering()
2575 return DAG.getBitcast(MVT::v4i8, R); in buildVector32()
[all …]
H A DHexagonRegisterInfo.td533 def IntRegs : RegisterClass<"Hexagon", [i32, f32, v4i8, v2i16], 32,
553 [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32, (add P0, P1, P2, P3)>;
H A DHexagonISelDAGToDAG.cpp102 case MVT::v4i8: in INITIALIZE_PASS()
492 case MVT::v4i8: in SelectIndexedStore()
/openbsd/gnu/llvm/llvm/lib/Target/SPIRV/
H A DSPIRVISelLowering.cpp43 return MVT::v4i8; in getRegisterTypeForCallingConv()
/openbsd/gnu/llvm/llvm/include/llvm/Support/
H A DMachineValueType.h87 v4i8 = 35, // 4 x i8 enumerator
411 return (SimpleTy == MVT::v32i1 || SimpleTy == MVT::v4i8 || in is32BitVector()
572 case v4i8: in getVectorElementType()
838 case v4i8: in getVectorMinNumElements()
967 case v4i8: in getSizeInBits()
1293 if (NumElements == 4) return MVT::v4i8; in getVectorVT()
/openbsd/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp509 {Intrinsic::vp_fshl, MVT::v4i8, 7},
547 {Intrinsic::vp_fshr, MVT::v4i8, 7},
585 {Intrinsic::bitreverse, MVT::v4i8, 17},
620 {Intrinsic::vp_bitreverse, MVT::v4i8, 17},
655 {Intrinsic::ctpop, MVT::v4i8, 12},
690 {Intrinsic::vp_ctpop, MVT::v4i8, 12},
725 {Intrinsic::vp_ctlz, MVT::v4i8, 19},
763 {Intrinsic::vp_cttz, MVT::v4i8, 16},
/openbsd/gnu/llvm/llvm/include/llvm/IR/
H A DIntrinsicsNVVM.td2574 "llvm.nvvm.suld.1d.v4i8.clamp">;
2664 "llvm.nvvm.suld.2d.v4i8.clamp">;
2754 "llvm.nvvm.suld.3d.v4i8.clamp">;
2800 "llvm.nvvm.suld.1d.v4i8.trap">;
2890 "llvm.nvvm.suld.2d.v4i8.trap">;
2980 "llvm.nvvm.suld.3d.v4i8.trap">;
3026 "llvm.nvvm.suld.1d.v4i8.zero">;
3116 "llvm.nvvm.suld.2d.v4i8.zero">;
3206 "llvm.nvvm.suld.3d.v4i8.zero">;
3605 "llvm.nvvm.sust.b.1d.v4i8.trap">,
[all …]
H A DIntrinsicsAMDGPU.td2164 // i32 %r = llvm.amdgcn.sdot4(v4i8 (as i32) %a, v4i8 (as i32) %b, i32 %c, i1 %clamp)
2194 // i32 %r = llvm.amdgcn.sudot4(i1 %a_sign, v4i8 (as i32) %a, i1 %b_sign, v4i8 (as i32) %b, i32 %c, …
/openbsd/gnu/llvm/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp537 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 0}, in getCastInstrCost()
538 {ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 0}, in getCastInstrCost()
573 {ISD::TRUNCATE, MVT::v4i32, MVT::v4i8, 0}, in getCastInstrCost()
657 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, in getCastInstrCost()
658 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, in getCastInstrCost()
690 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
691 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
705 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, in getCastInstrCost()
706 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 }, in getCastInstrCost()
803 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, in getCastInstrCost()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2087 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, in getCastInstrCost()
2106 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, in getCastInstrCost()
2124 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, in getCastInstrCost()
2239 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 }, in getCastInstrCost()
2240 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 }, in getCastInstrCost()
2335 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, in getCastInstrCost()
2352 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, in getCastInstrCost()
2370 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, in getCastInstrCost()
4956 { ISD::ADD, MVT::v4i8, 2 }, in getArithmeticReductionCost()
5343 {ISD::SMIN, MVT::v4i8, 5}, // pminsb in getMinMaxReductionCost()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp1828 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1}, // xtn in getCastInstrCost()
1829 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 3}, // 2 xtn + 1 uzp1 in getCastInstrCost()
1899 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 }, in getCastInstrCost()
1901 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
1944 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 }, in getCastInstrCost()
1946 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 2 }, in getCastInstrCost()
2083 {ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f16, 1}, // fcvtzs in getCastInstrCost()
2084 {ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f16, 1}, in getCastInstrCost()
2307 {ISD::SDIV, MVT::v2i8, 5}, {ISD::SDIV, MVT::v4i8, 8}, in getArithmeticInstrCost()
2310 {ISD::UDIV, MVT::v2i8, 5}, {ISD::UDIV, MVT::v4i8, 8}, in getArithmeticInstrCost()
[all …]
/openbsd/gnu/gcc/gcc/doc/
H A Dextend.texi7362 v4i8 __builtin_mips_addu_qb (v4i8, v4i8)
7363 v4i8 __builtin_mips_addu_s_qb (v4i8, v4i8)
7367 v4i8 __builtin_mips_subu_qb (v4i8, v4i8)
7368 v4i8 __builtin_mips_subu_s_qb (v4i8, v4i8)
7389 v4i8 __builtin_mips_shll_qb (v4i8, imm0_7)
7390 v4i8 __builtin_mips_shll_qb (v4i8, i32)
7397 v4i8 __builtin_mips_shrl_qb (v4i8, imm0_7)
7398 v4i8 __builtin_mips_shrl_qb (v4i8, i32)
7429 void __builtin_mips_cmpu_eq_qb (v4i8, v4i8)
7430 void __builtin_mips_cmpu_lt_qb (v4i8, v4i8)
[all …]
H A Dgcc.info21754 v4i8 __builtin_mips_addu_qb (v4i8, v4i8)
21755 v4i8 __builtin_mips_addu_s_qb (v4i8, v4i8)
21759 v4i8 __builtin_mips_subu_qb (v4i8, v4i8)
21760 v4i8 __builtin_mips_subu_s_qb (v4i8, v4i8)
21781 v4i8 __builtin_mips_shll_qb (v4i8, imm0_7)
21782 v4i8 __builtin_mips_shll_qb (v4i8, i32)
21789 v4i8 __builtin_mips_shrl_qb (v4i8, imm0_7)
21790 v4i8 __builtin_mips_shrl_qb (v4i8, i32)
21821 void __builtin_mips_cmpu_eq_qb (v4i8, v4i8)
21822 void __builtin_mips_cmpu_lt_qb (v4i8, v4i8)
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td267 defm VR32 : SystemZRegClass<"VR32", [f32, v4i8, v2i16], 32,
/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/
H A DValueTypes.td60 def v4i8 : ValueType<32, 35>; // 4 x i8 vector value
/openbsd/gnu/llvm/llvm/utils/TableGen/
H A DCodeGenTarget.cpp101 case MVT::v4i8: return "MVT::v4i8"; in getEnumName()
/openbsd/gnu/llvm/llvm/lib/CodeGen/
H A DValueTypes.cpp249 case MVT::v4i8: in getTypeForEVT()
/openbsd/gnu/llvm/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp127 case MVT::v4i8: in IsPTXVectorType()
2492 case MVT::v4i8: in LowerSTOREVector()
4823 if (MemVT != MVT::v2i8 && MemVT != MVT::v4i8) { in PerformANDCombine()
5117 case MVT::v4i8: in ReplaceLoadVector()
/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp77 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom); in R600TargetLowering()
132 setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::v2i8, MVT::v4i8}, Expand); in R600TargetLowering()

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