1 /* 2 * Copyright (c) 1982, 1986 Regents of the University of California. 3 * All rights reserved. The Berkeley software License Agreement 4 * specifies the terms and conditions for redistribution. 5 * 6 * @(#)upreg.h 7.1 (Berkeley) 06/05/86 7 */ 8 9 /* 10 * Unibus rm emulation via sc21: 11 * registers and bits. 12 */ 13 14 struct updevice 15 { 16 u_short upcs1; /* control and status register 1 */ 17 short upwc; /* word count register */ 18 u_short upba; /* UNIBUS address register */ 19 u_short upda; /* desired address register */ 20 u_short upcs2; /* control and status register 2 */ 21 u_short upds; /* drive Status */ 22 u_short uper1; /* error register 1 */ 23 u_short upas; /* attention summary */ 24 u_short upla; /* look ahead */ 25 u_short updb; /* data buffer */ 26 u_short upmr; /* maintenance */ 27 u_short updt; /* drive type */ 28 u_short upsn; /* serial number */ 29 u_short upof; /* offset register */ 30 u_short updc; /* desired cylinder address register */ 31 u_short uphr; /* holding register */ 32 u_short upmr2; /* maintenance register 2 */ 33 u_short uper2; /* error register 2 */ 34 u_short upec1; /* burst error bit position */ 35 u_short upec2; /* burst error bit pattern */ 36 }; 37 38 /* Other bits of upcs1 */ 39 #define UP_SC 0100000 /* special condition */ 40 #define UP_TRE 0040000 /* transfer error */ 41 #define UP_PSEL 0010000 /* port select */ 42 #define UP_DVA 0004000 /* drive available */ 43 /* bits 8 and 9 are the extended address bits */ 44 #define UP_RDY 0000200 /* controller ready */ 45 #define UP_IE 0000100 /* interrupt enable */ 46 /* bits 5-1 are the command */ 47 #define UP_GO 0000001 48 49 /* commands */ 50 #define UP_NOP 000 51 #define UP_SEEK 004 /* seek */ 52 #define UP_RECAL 006 /* recalibrate */ 53 #define UP_DCLR 010 /* drive clear */ 54 #define UP_RELEASE 012 /* release */ 55 #define UP_OFFSET 014 /* offset */ 56 #define UP_RTC 016 /* return to center-line */ 57 #define UP_PRESET 020 /* read-in preset */ 58 #define UP_PACK 022 /* pack acknowledge */ 59 #define UP_DMABAND 024 /* dma bandwidth set */ 60 #define UP_SEARCH 030 /* search */ 61 #define UP_WCDATA 050 /* write check data */ 62 #define UP_WCHDR 052 /* write check header and data */ 63 #define UP_WCOM 060 /* write */ 64 #define UP_WHDR 062 /* write header and data */ 65 #define UP_RCOM 070 /* read data */ 66 #define UP_RHDR 072 /* read header and data */ 67 #define UP_BOOT 074 /* boot */ 68 #define UP_FORMAT 076 /* format */ 69 70 /* upcs2 */ 71 #define UPCS2_DLT 0100000 /* data late */ 72 #define UPCS2_WCE 0040000 /* write check error */ 73 #define UPCS2_UPE 0020000 /* UNIBUS parity error */ 74 #define UPCS2_NED 0010000 /* nonexistent drive */ 75 #define UPCS2_NEM 0004000 /* nonexistent memory */ 76 #define UPCS2_PGE 0002000 /* programming error */ 77 #define UPCS2_MXF 0001000 /* missed transfer */ 78 #define UPCS2_MDPE 0000400 /* massbus data parity error (0) */ 79 #define UPCS2_OR 0000200 /* output ready */ 80 #define UPCS2_IR 0000100 /* input ready */ 81 #define UPCS2_CLR 0000040 /* controller clear */ 82 #define UPCS2_PAT 0000020 /* parity test */ 83 #define UPCS2_BAI 0000010 /* address increment inhibit */ 84 /* bits 0-2 are drive select */ 85 86 #define UPCS2_BITS \ 87 "\10\20DLT\17WCE\16UPE\15NED\14NEM\13PGE\12MXF\11MDPE\ 88 \10OR\7IR\6CLR\5PAT\4BAI" 89 90 /* upds */ 91 #define UPDS_ATA 0100000 /* attention active */ 92 #define UPDS_ERR 0040000 /* composite drive error */ 93 #define UPDS_PIP 0020000 /* positioning in progress */ 94 #define UPDS_MOL 0010000 /* medium on line */ 95 #define UPDS_WRL 0004000 /* write locked */ 96 #define UPDS_LST 0002000 /* last sector transferred */ 97 #define UPDS_PGM 0001000 /* programmable */ 98 #define UPDS_DPR 0000400 /* drive present */ 99 #define UPDS_DRY 0000200 /* drive ready */ 100 #define UPDS_VV 0000100 /* volume valid */ 101 /* bits 1-5 are spare */ 102 #define UPDS_OM 0000001 /* offset mode */ 103 104 #define UPDS_DREADY (UPDS_DPR|UPDS_DRY|UPDS_MOL|UPDS_VV) 105 106 #define UPDS_BITS \ 107 "\10\20ATA\17ERR\16PIP\15MOL\14WRL\13LST\12PGM\11DPR\10DRY\7VV\1OM" 108 109 /* uper1 */ 110 #define UPER1_DCK 0100000 /* data check */ 111 #define UPER1_UNS 0040000 /* drive unsafe */ 112 #define UPER1_OPI 0020000 /* operation incomplete */ 113 #define UPER1_DTE 0010000 /* drive timing error */ 114 #define UPER1_WLE 0004000 /* write lock error */ 115 #define UPER1_IAE 0002000 /* invalid address error */ 116 #define UPER1_AOE 0001000 /* address overflow error */ 117 #define UPER1_HCRC 0000400 /* header crc error */ 118 #define UPER1_HCE 0000200 /* header compare error */ 119 #define UPER1_ECH 0000100 /* ecc hard error */ 120 #define UPER1_WCF 0000040 /* write clock fail (0) */ 121 #define UPER1_FER 0000020 /* format error */ 122 #define UPER1_PAR 0000010 /* parity error */ 123 #define UPER1_RMR 0000004 /* register modification refused */ 124 #define UPER1_ILR 0000002 /* illegal register */ 125 #define UPER1_ILF 0000001 /* illegal function */ 126 127 #define UPER1_BITS \ 128 "\10\20DCK\17UNS\16OPI\15DTE\14WLE\13IAE\12AOE\11HCRC\10HCE\ 129 \7ECH\6WCF\5FER\4PAR\3RMR\2ILR\1ILF" 130 131 /* uphr */ 132 /* write these int uphr and then read back values */ 133 #define UPHR_MAXCYL 0100027 /* max cyl address */ 134 #define UPHR_MAXTRAK 0100030 /* max track address */ 135 #define UPHR_MAXSECT 0100031 /* max sector address */ 136 137 /* uper2 */ 138 #define UPER2_BSE 0100000 /* bad sector error */ 139 #define UPER2_SKI 0040000 /* seek incomplete */ 140 #define UPER2_OPE 0020000 /* operator plug error */ 141 #define UPER2_IVC 0010000 /* invalid command */ 142 #define UPER2_LSC 0004000 /* loss of sector clock */ 143 #define UPER2_LBC 0002000 /* loss of bit clock */ 144 #define UPER2_MDS 0001000 /* multiple drive select */ 145 #define UPER2_DCU 0000400 /* dc power unsafe */ 146 #define UPER2_DVC 0000200 /* device check */ 147 #define UPER2_ACU 0000100 /* ac power unsafe */ 148 /* bits 5 and 4 are spare */ 149 #define UPER2_DPE 0000010 /* data parity error (0) */ 150 /* bits 2-0 are spare */ 151 152 #define UPER2_BITS \ 153 "\10\20BSE\17SKI\16OPE\15IVC\14LSC\13LBC\12MDS\11DCU\10DVC\7ACU\4DPE" 154 155 /* upof */ 156 #define UPOF_FMT22 0010000 /* 16 bit format */ 157 #define UPOF_ECI 0004000 /* ecc inhibit */ 158 #define UPOF_HCI 0002000 /* header compare inhibit */ 159 160 /* THE SC21 ACTUALLY JUST IMPLEMENTS ADVANCE/RETARD... */ 161 #define UPOF_P400 0020 /* +400 uinches */ 162 #define UPOF_M400 0220 /* -400 uinches */ 163 #define UPOF_P800 0040 /* +800 uinches */ 164 #define UPOF_M800 0240 /* -800 uinches */ 165 #define UPOF_P1200 0060 /* +1200 uinches */ 166 #define UPOF_M1200 0260 /* -1200 uinches */ 167