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Searched refs:WR2 (Results 1 – 5 of 5) sorted by relevance

/original-bsd/sys/luna68k/stand/
H A Dsioreg.h35 #define WR2 0x02 macro
/original-bsd/sys/luna68k/dev/
H A Dsioreg.h38 #define WR2 0x02 macro
H A Dsio.c616 sioreg(sio0, WR2, (WR2_VEC86 | WR2_INTR_1)); /* Set CPU BUS Interface Mode */
617 sioreg(sio1, WR2, 0); /* Set Interrupt Vector */
/original-bsd/sys/news3400/sio/
H A Dsccreg.h81 #define WR2 2 macro
H A Dscc.c159 scc_write_reg(chan, WR2, scc->scc_vec & ~0x0f);