Home
last modified time | relevance | path

Searched refs:csr (Results 1 – 25 of 47) sorted by relevance

12

/original-bsd/sys/tahoe/conf/
H A DGENERIC.tahoe32 controller vd0 at vba? csr 0xffff2000 vector vdintr
37 controller vd1 at vba? csr 0xffff2100 vector vdintr
42 controller vd2 at vba? csr 0xffff2200 vector vdintr
48 controller cy0 at vba? csr 0xffff4000 vector cyintr
53 controller cy1 at vba? csr 0xffff6000 vector cyintr
76 device mp0 at vba? csr 0xffff5000 vector mpintr mpdlintr
77 device mp1 at vba? csr 0xffff5100 vector mpintr mpdlintr
85 device enp0 at vba? csr 0xfff41000 vector enpintr
86 device enp1 at vba? csr 0xfff61000 vector enpintr
88 device dr0 at vba? csr 0xffff7000 vector drintr
[all …]
H A DGENERIC.alltahoe35 controller vd0 at vba? csr 0xffff2000 vector vdintr
40 controller vd1 at vba? csr 0xffff2100 vector vdintr
45 controller vd2 at vba? csr 0xffff2200 vector vdintr
51 controller cy0 at vba? csr 0xffff4000 vector cyintr
56 controller cy1 at vba? csr 0xffff6000 vector cyintr
74 device enp0 at vba? csr 0xfff41000 vector enpintr
75 device enp1 at vba? csr 0xfff61000 vector enpintr
77 device dr0 at vba? csr 0xffff7000 vector drintr
78 device ik0 at vba? csr 0xffff8000 vector ikintr
81 controller hdc0 at vba? csr 0xC5010000 vector hdintr
[all …]
H A DGENERIC.hcx933 controller hdc0 at vba? csr 0xC5010000 vector hdintr
38 controller hdc1 at vba? csr 0xC6010000 vector hdintr
44 device vx0 at vba? csr 0xcd020000 vector vxintr
45 device vx1 at vba? csr 0xce020000 vector vxintr
51 device ex0 at vba? csr 0xfff00000 vector exintr
/original-bsd/sys/vax/conf/
H A DGENERIC.allvax63 controller kdb0 at bi0 csr 0 vector kdbintr
70 controller hk0 at uba? csr 0177440 vector rkintr
76 controller tm0 at uba? csr 0172520 vector tmintr
80 controller ut0 at uba? csr 0172440 vector utintr
109 device dm0 at uba? csr 0170500 vector dmintr
124 device dmf0 at uba? csr 0160340 flags 0xfc
131 device lp0 at uba? csr 0177514 vector lpintr
140 device ec0 at uba? csr 0164330 flags 0
142 device de0 at uba? csr 0174510 vector deintr
144 device ex0 at uba? csr 0164344 vector excdint
[all …]
H A DGENERIC.vaxminiroot50 controller kdb0 at bi0 csr 0 vector kdbintr
57 controller hk0 at uba? csr 0177440 vector rkintr
63 controller tm0 at uba? csr 0172520 vector tmintr
67 controller ut0 at uba? csr 0172440 vector utintr
96 device dm0 at uba? csr 0170500 vector dmintr
111 device dmf0 at uba? csr 0160340 flags 0xfc
118 device lp0 at uba? csr 0177514 vector lpintr
127 device ec0 at uba? csr 0164330 flags 0
129 device de0 at uba? csr 0174510 vector deintr
131 device ex0 at uba? csr 0164344 vector excdint
[all …]
H A DGENERIC.vax61 controller kdb0 at bi0 csr 0 vector kdbintr
68 controller hk0 at uba? csr 0177440 vector rkintr
74 controller tm0 at uba? csr 0172520 vector tmintr
78 controller ut0 at uba? csr 0172440 vector utintr
102 controller hl0 at uba? csr 0174400 vector rlintr
107 device dm0 at uba? csr 0170500 vector dmintr
122 device dmf0 at uba? csr 0160340 flags 0xfc
129 device lp0 at uba? csr 0177514 vector lpintr
135 device ec0 at uba? csr 0164330 flags 0
137 device de0 at uba? csr 0174510 vector deintr
[all …]
/original-bsd/sys/sparc/sbus/
H A Ddmareg.h52 #define DMA_REV(csr) (((csr) >> 28) & 0xf) /* device id field */ argument
102 #define DMA_BYTE(csr) (((csr) >> 11) & 3) argument
105 #define DMA_NPACK(csr) (((csr) >> 2) & 3) argument
108 #define DMA_INTR(csr) ((csr) & (DMA_IP | DMA_EP)) argument
/original-bsd/sys/pmax/conf/
H A DGENERIC.pmax57 controller dtop0 at nexus0 csr ?
58 controller dc0 at nexus0 csr ?
59 controller xcfb0 at nexus0 csr ?
60 controller cfb0 at nexus0 csr ?
61 controller mfb0 at nexus0 csr ?
62 controller pm0 at nexus0 csr ?
63 controller scc0 at nexus0 csr ?
64 controller scc1 at nexus0 csr ?
65 controller le0 at nexus0 csr ?
66 master sii0 at nexus0 csr ?
[all …]
H A DMAXP57 controller dtop0 at nexus0 csr ?
58 controller dc0 at nexus0 csr ?
59 controller xcfb0 at nexus0 csr ?
60 controller cfb0 at nexus0 csr ?
61 controller mfb0 at nexus0 csr ?
62 controller pm0 at nexus0 csr ?
63 controller scc0 at nexus0 csr ?
64 controller scc1 at nexus0 csr ?
65 controller le0 at nexus0 csr ?
66 master sii0 at nexus0 csr ?
[all …]
/original-bsd/sys/vax/if/
H A Dif_accreg.h15 short csr; /* control and status */ member
26 #define icsr input.csr
29 #define ocsr output.csr
H A Dif_cssreg.h17 short csr; /* status register */ member
27 #define css_icsr css_input.csr
30 #define css_ocsr css_output.csr
H A Dif_il.c361 short csr; local
370 csr = ((is->is_ubaddr >> 2) & IL_EUA)|ILC_STAT|IL_RIE|IL_CIE;
388 csr =
392 is->is_lastcmd = csr & IL_CMD;
393 addr->il_csr = csr;
407 short csr; local
415 csr = addr->il_csr;
434 csr &= IL_STATUS;
439 if (csr > ILERR_RETRIES)
444 if (csr == ILERR_SUCCESS)
H A Dif_hdh.c198 addr->csr = (short) HDH_RST;
199 addr->csr = (short) (HDH_IEN|HDH_DMA|HDH_WRT); /* set enables */
438 addr->csr = HDH_DMA|HDH_WRT|HDH_IEN|HDH_NMI;
456 if (addr->csr & HDH_UER) {
457 printf("hdh%d: hard error csr=%b\n", unit, addr->csr, HDH_BITS);
458 addr->csr = 0; /* disable i/f */
536 addr->csr = HDH_DMA|HDH_WRT|HDH_IEN|HDH_NMI;
H A Dif_acp.c463 addr->csr = CSR_RESET; /* reset the board */
464 addr->csr |= CSR_IENB; /* enable status intr */
558 addr->csr = CSR_RESET; /* reset the board */
559 addr->csr |= CSR_IENB; /* enable status intr */
1062 addr->csr |= CSR_INTRA;
1135 addr->csr |= CSR_INTRA; /* enable interrupt "a" */
1176 addr->csr = 0;
1186 addr->csr = 0;
1191 addr->csr |= (CSR_IENA | CSR_DMAEN);
1562 addr->csr |= CSR_INTRA;
/original-bsd/sys/vax/uba/
H A Ddmx.c93 sc->dmx_octet->csr |= DMF_IE;
181 addr->csr = DMF_IE | DMFIR_LCR | unit;
282 addr->csr = DMF_IE | DMFIR_LCR | unit;
378 addr->csr = unit | DMFIR_LCR | DMF_IE;
417 while ((t = addr->csr) & DMF_TI) {
436 addr->csr = DMFIR_TBA | DMF_IE | t;
475 addr->csr = DMF_IE | DMFIR_TBUF | unit;
481 addr->csr = DMF_IE | DMFIR_LCR | unit;
527 addr->csr = DMF_IE | DMFIR_LCR | unit;
530 addr->csr = DMF_IE | DMFIR_TBA | unit;
[all …]
H A Dqd.c683 dga->csr |= CURS_ENB;
775 dga->csr &= ~DMA_IE;
785 dga->csr |= DMA_IE;
842 dga->csr &= ~DMA_IE;
853 dga->csr |= DMA_IE;
854 dga->csr &= ~DMA_IE;
1467 dga->csr |= DMA_IE;
1487 dga->csr &= ~DMA_IE;
1499 dga->csr |= DMA_IE;
1912 dga->csr |= DL_ENB;
[all …]
H A Ddhureg.h14 short csr; /* control-status register */ member
20 #define dhucsr un1.csr
/original-bsd/sys/vax/vax/
H A Dka820.c49 register int csr; in ka820_init() local
63 csr = ka820port.csr; in ka820_init()
64 csr &= ~KA820PORT_RSTHALT; /* ??? */ in ka820_init()
65 csr |= KA820PORT_CONSCLR | KA820PORT_CRDCLR | KA820PORT_CONSEN | in ka820_init()
67 ka820port.csr = csr; in ka820_init()
/original-bsd/sys/pmax/dev/
H A Dxcfb.c425 register u_int csr;
437 csr = ims332_read_register(IMS332_REG_CSR_A);
438 csr |= IMS332_CSR_A_DISABLE_CURSOR;
439 ims332_write_register(IMS332_REG_CSR_A, csr);
447 register u_int csr;
457 csr = ims332_read_register(IMS332_REG_CSR_A);
458 csr &= ~IMS332_CSR_A_DISABLE_CURSOR;
459 ims332_write_register(IMS332_REG_CSR_A, csr);
H A Dascreg.h203 #define ASC_PHASE(csr) ((csr) & 0x7) argument
/original-bsd/sys/tahoe/vba/
H A Dik.c358 u_short bc, csr; local
405 csr = IKCSR_CYCLE;
410 csr = IKCSR_CYCLE|IKCSR_FNC1;
425 ik->ik_csr = IKCSR_IENA|IKCSR_GO|csr;
624 register u_short csr; local
634 csr = ik->ik_csr;
636 if ((csr&IKCSR_DONE) == IKCSR_DONE) {
645 if ((csr&(IKCSR_ATTF|IKCSR_STATC)) == IKCSR_ATTF)
/original-bsd/sys/vax/datakit/
H A Dkmc.c292 short csr[4]; local
338 csr[0] = kp->sel0;
339 csr[1] = kp->sel2;
340 csr[2] = kp->sel4;
341 csr[3] = kp->sel6;
342 if (copyout((caddr_t)csr, (caddr_t)kk->kcsr, sizeof csr))
/original-bsd/sys/tahoe/if/
H A Dif_ace.c107 movow(&ap->csr, CSR_RESET);
209 movow(&addr->csr, CSR_RESET);
217 movow(&addr->csr, CSR_GO);
218 Csr = addr->csr;
222 movow(&addr->csr, Csr);
647 movow(&addr->csr, CSR_RESET);
668 movow(&addr->csr, CSR_RESET);
H A Dif_acereg.h24 short csr; /* control and status register */ member
/original-bsd/sys/pmax/pmax/
H A Dtrap.c859 register unsigned csr; local
866 csr = *(unsigned *)MACH_PHYS_TO_UNCACHED(KN02_SYS_CSR);
867 if ((csr & KN02_CSR_PSWARN) && !warned) {
870 } else if (warned && !(csr & KN02_CSR_PSWARN)) {
890 m = csr & (csr >> KN02_CSR_IOINTEN_SHIFT) & KN02_CSR_IOINT;
893 (csr & ~(KN02_CSR_WRESERVED | 0xFF)) |
907 csr & ~(KN02_CSR_WRESERVED | 0xFF);
1310 u_short csr; in pmax_errintr() local
1312 csr = *sysCSRPtr; in pmax_errintr()
1314 if (csr & KN01_CSR_MERR) { in pmax_errintr()
[all …]

12