1 /* 2 * Copyright (c) 1988 University of Utah. 3 * Copyright (c) 1990, 1993 4 * The Regents of the University of California. All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * the Systems Programming Group of the University of Utah Computer 8 * Science Department. 9 * 10 * %sccs.include.redist.c% 11 * 12 * from: Utah $Hdr: grf_rbreg.h 1.9 92/01/21$ 13 * 14 * @(#)grf_rbreg.h 8.1 (Berkeley) 06/10/93 15 */ 16 17 /* 18 * Map of the Renaissance frame buffer controller chip in memory ... 19 */ 20 21 #include <hp/dev/iotypes.h> /* XXX */ 22 23 #define rb_waitbusy(regaddr) \ 24 while (((struct rboxfb *)(regaddr))->wbusy & 0x01) DELAY(100) 25 26 #define CM1RED ((struct rencm *)(ip->regbase + 0x6400)) 27 #define CM1GRN ((struct rencm *)(ip->regbase + 0x6800)) 28 #define CM1BLU ((struct rencm *)(ip->regbase + 0x6C00)) 29 #define CM2RED ((struct rencm *)(ip->regbase + 0x7400)) 30 #define CM2GRN ((struct rencm *)(ip->regbase + 0x7800)) 31 #define CM2BLU ((struct rencm *)(ip->regbase + 0x7C00)) 32 33 struct rencm { 34 u_char :8, :8, :8; 35 vu_char value; 36 }; 37 38 struct rboxfb { 39 u_char filler1[1]; 40 vu_char reset; /* reset register 0x01 */ 41 vu_char fb_address; /* frame buffer address 0x02 */ 42 vu_char interrupt; /* interrupt register 0x03 */ 43 u_char filler1a; 44 vu_char fbwmsb; /* frame buffer width MSB 0x05 */ 45 u_char filler1b; 46 vu_char fbwlsb; /* frame buffer width MSB 0x07 */ 47 u_char filler1c; 48 vu_char fbhmsb; /* frame buffer height MSB 0x09 */ 49 u_char filler1d; 50 vu_char fbhlsb; /* frame buffer height MSB 0x0b */ 51 u_char filler1e; 52 vu_char dwmsb; /* display width MSB 0x0d */ 53 u_char filler1f; 54 vu_char dwlsb; /* display width MSB 0x0f */ 55 u_char filler1g; 56 vu_char dhmsb; /* display height MSB 0x11 */ 57 u_char filler1h; 58 vu_char dhlsb; /* display height MSB 0x13 */ 59 u_char filler1i; 60 vu_char fbid; /* frame buffer id 0x15 */ 61 u_char filler1j[0x47]; 62 vu_char fbomsb; /* frame buffer offset MSB 0x5d */ 63 u_char filler1k; 64 vu_char fbolsb; /* frame buffer offset LSB 0x5f */ 65 u_char filler2[16359]; 66 vu_char wbusy; /* window mover is active 0x4047 */ 67 u_char filler3[0x405b - 0x4048]; 68 vu_char scanbusy; /* scan converteris active 0x405B */ 69 u_char filler3b[0x4083 - 0x405c]; 70 vu_char video_enable; /* drive vid. refresh bus 0x4083 */ 71 u_char filler4[3]; 72 vu_char display_enable; /* enable the display 0x4087 */ 73 u_char filler5[8]; 74 vu_int write_enable; /* write enable register 0x4090 */ 75 u_char filler6[11]; 76 vu_char wmove; /* start window mover 0x409f */ 77 u_char filler7[3]; 78 vu_char blink; /* blink register 0x40a3 */ 79 u_char filler8[15]; 80 vu_char fold; /* fold register 0x40b3 */ 81 vu_int opwen; /* overlay plane write enable 0x40b4 */ 82 u_char filler9[3]; 83 vu_char tmode; /* Tile mode size 0x40bb */ 84 u_char filler9a[3]; 85 vu_char drive; /* drive register 0x40bf */ 86 u_char filler10[3]; 87 vu_char vdrive; /* vdrive register 0x40c3 */ 88 u_char filler10a[0x40cb-0x40c4]; 89 vu_char zconfig; /* Z-buffer mode 0x40cb */ 90 u_char filler11a[2]; 91 vu_short tpatt; /* Transparency pattern 0x40ce */ 92 u_char filler11b[3]; 93 vu_char dmode; /* dither mode 0x40d3 */ 94 u_char filler11c[3]; 95 vu_char en_scan; /* enable scan board to DTACK 0x40d7 */ 96 u_char filler11d[0x40ef-0x40d8]; 97 vu_char rep_rule; /* replacement rule 0x40ef */ 98 u_char filler12[2]; 99 vu_short source_x; /* source x 0x40f2 */ 100 u_char filler13[2]; 101 vu_short source_y; /* source y 0x40f6 */ 102 u_char filler14[2]; 103 vu_short dest_x; /* dest x 0x40fa */ 104 u_char filler15[2]; 105 vu_short dest_y; /* dest y 0x40fe */ 106 u_char filler16[2]; 107 vu_short wwidth; /* window width 0x4102 */ 108 u_char filler17[2]; 109 vu_short wheight; /* window height 0x4106 */ 110 u_char filler18[18]; 111 vu_short patt_x; /* pattern x 0x411a */ 112 u_char filler19[2]; 113 vu_short patt_y; /* pattern y 0x411e */ 114 u_char filler20[0x8012 - 0x4120]; 115 vu_short te_status; /* transform engine status 0x8012 */ 116 u_char filler21[0x1ffff-0x8014]; 117 }; 118