/qemu/tests/tcg/hexagon/ |
H A D | load_align.c | 138 checkp(ptr, &buf[0 * (SIZE)]); \ 141 checkp(ptr, &buf[1 * (SIZE)]); \ 144 checkp(ptr, &buf[2 * (SIZE)]); \ 147 checkp(ptr, &buf[3 * (SIZE)]); \ 178 LOAD_pr_##SZ(result, ptr, (SIZE)); \ 180 checkp(ptr, &buf[1 * (SIZE)]); \ 181 LOAD_pr_##SZ(result, ptr, (SIZE)); \ 183 checkp(ptr, &buf[2 * (SIZE)]); \ 184 LOAD_pr_##SZ(result, ptr, (SIZE)); \ 186 checkp(ptr, &buf[3 * (SIZE)]); \ [all …]
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H A D | load_unpack.c | 153 checkp(ptr, &buf[0 * (SIZE)]); \ 156 checkp(ptr, &buf[1 * (SIZE)]); \ 159 checkp(ptr, &buf[2 * (SIZE)]); \ 162 checkp(ptr, &buf[3 * (SIZE)]); \ 198 BxW_LOAD_pr_##SIGN(result, ptr, (SIZE)); \ 200 checkp(ptr, &buf[1 * (SIZE)]); \ 201 BxW_LOAD_pr_##SIGN(result, ptr, (SIZE)); \ 203 checkp(ptr, &buf[2 * (SIZE)]); \ 204 BxW_LOAD_pr_##SIGN(result, ptr, (SIZE)); \ 206 checkp(ptr, &buf[3 * (SIZE)]); \ [all …]
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H A D | brev.c | 27 #define SIZE (1 << NBITS) macro 29 int64_t dbuf[SIZE] __attribute__((aligned(1 << 16))) = {0}; 30 int32_t wbuf[SIZE] __attribute__((aligned(1 << 16))) = {0}; 31 int16_t hbuf[SIZE] __attribute__((aligned(1 << 16))) = {0}; 115 for (int i = 0; i < SIZE; i++) { \ 126 for (int i = 0; i < SIZE; i++) { \ 129 for (int i = 0; i < SIZE; i++) { \ 138 for (int i = 0; i < SIZE; i++) { \ 141 for (int i = 0; i < SIZE; i++) { \ 150 int high_half[SIZE]; [all …]
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H A D | circ.c | 69 #define CIRC_LOAD_IMM(SIZE, RES, ADDR, START, LEN, INC) \ in INIT() argument 74 "%0 = mem" #SIZE "(%1++#" #INC ":circ(M0))\n\t" \ in INIT() 106 #define CIRC_LOAD_REG(SIZE, RES, ADDR, START, LEN, INC) \ argument 111 "%0 = mem" #SIZE "(%1++I:circ(M1))\n\t" \ 137 #define CIRC_STORE_IMM(SIZE, PART, VAL, ADDR, START, LEN, INC) \ argument 142 "mem" #SIZE "(%0++#" #INC ":circ(M0)) = %2" PART "\n\t" \ 157 #define CIRC_STORE_NEW_IMM(SIZE, VAL, ADDR, START, LEN, INC) \ argument 176 #define CIRC_STORE_REG(SIZE, PART, VAL, ADDR, START, LEN, INC) \ argument 181 "mem" #SIZE "(%0++I:circ(M1)) = %3" PART "\n\t" \ 198 #define CIRC_STORE_NEW_REG(SIZE, VAL, ADDR, START, LEN, INC) \ argument [all …]
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/qemu/tests/qemu-iotests/tests/ |
H A D | parallels-checks | 44 SIZE=$((4 * 1024 * 1024)) 50 _make_test_img $SIZE 54 LAST_CLUSTER_OFF=$((SIZE - CLUSTER_SIZE)) 60 { $QEMU_IO -c "write -P 0x11 0 $SIZE" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir 70 _make_test_img $SIZE 97 _make_test_img $SIZE 102 { $QEMU_IO -c "write -P 0x11 0 $SIZE" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir 136 _make_test_img $SIZE 141 { $QEMU_IO -c "write -P 0x11 0 $SIZE" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir 172 _make_test_img $SIZE [all …]
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H A D | qcow2-internal-snapshots.out | 18 1 snap0 SIZE yyyy-mm-dd hh:mm:ss 0000:00:00.000 -- 51 1 snap0 SIZE yyyy-mm-dd hh:mm:ss 0000:00:00.000 -- 52 2 snap1 SIZE yyyy-mm-dd hh:mm:ss 0000:00:00.000 -- 83 1 snap0 SIZE yyyy-mm-dd hh:mm:ss 0000:00:00.000 --
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/qemu/scripts/coccinelle/ |
H A D | memory-region-housekeeping.cocci | 75 expression SIZE; 78 -memory_region_init_ram_nomigrate(MR, NULL, NAME, SIZE, ERRP); 79 +memory_region_init_ram(MR, NULL, NAME, SIZE, ERRP); 85 expression SIZE; 88 -memory_region_init_rom_nomigrate(MR, NULL, NAME, SIZE, ERRP); 89 +memory_region_init_rom(MR, NULL, NAME, SIZE, ERRP); 97 expression SIZE; 100 -memory_region_init_rom_device_nomigrate(MR, NULL, OPS, OPAQUE, NAME, SIZE, ERRP); 101 +memory_region_init_rom_device(MR, NULL, OPS, OPAQUE, NAME, SIZE, ERRP);
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/qemu/tests/qemu-iotests/ |
H A D | 191.out | 131 "actual-size": SIZE, 162 "actual-size": SIZE, 200 "actual-size": SIZE, 231 "actual-size": SIZE, 269 "actual-size": SIZE, 300 "actual-size": SIZE, 329 "actual-size": SIZE, 357 "actual-size": SIZE, 538 "actual-size": SIZE, 569 "actual-size": SIZE, [all …]
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H A D | 273.out | 32 "actual-size": SIZE, 40 "actual-size": SIZE, 50 "actual-size": SIZE, 81 "actual-size": SIZE, 110 "actual-size": SIZE, 118 "actual-size": SIZE, 149 "actual-size": SIZE, 177 "actual-size": SIZE,
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H A D | 267.out | 37 -- snap0 SIZE yyyy-mm-dd hh:mm:ss 0000:00:00.000 -- 48 -- snap0 SIZE yyyy-mm-dd hh:mm:ss 0000:00:00.000 -- 73 -- snap0 SIZE yyyy-mm-dd hh:mm:ss 0000:00:00.000 -- 98 -- snap0 SIZE yyyy-mm-dd hh:mm:ss 0000:00:00.000 -- 109 -- snap0 SIZE yyyy-mm-dd hh:mm:ss 0000:00:00.000 -- 123 -- snap0 SIZE yyyy-mm-dd hh:mm:ss 0000:00:00.000 -- 138 -- snap0 SIZE yyyy-mm-dd hh:mm:ss 0000:00:00.000 -- 149 -- snap0 SIZE yyyy-mm-dd hh:mm:ss 0000:00:00.000 -- 156 1 snap0 SIZE yyyy-mm-dd hh:mm:ss 0000:00:00.000 -- 170 -- snap0 SIZE yyyy-mm-dd hh:mm:ss 0000:00:00.000 -- [all …]
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H A D | 313.out | 5 Formatting 'TEST_DIR/t.IMGFMT.base', fmt=IMGFMT size=SIZE 14 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=SIZE backing_file=TEST_DIR/t.IMGFMT.base backing_fm…
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H A D | 257 | 29 SIZE = 64 * 1024 * 1024 variable 295 drive0.img_create(iotests.imgfmt, SIZE) 398 ebitmap.dirty_bits(range(fail_bit, SIZE // GRANULARITY)) 452 drive0.img_create(iotests.imgfmt, SIZE)
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H A D | 190.out | 20 required size: SIZE
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H A D | common.filter | 121 gsed -s 's/\("actual-size":\s*\)[0-9]\+/\1SIZE/g'
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H A D | 109.out | 6 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=SIZE 57 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=SIZE 108 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=SIZE 159 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=SIZE 210 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=SIZE 261 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=SIZE 311 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=SIZE 361 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=SIZE 411 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=SIZE 461 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=SIZE [all …]
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/qemu/target/hexagon/ |
H A D | macros.h | 86 #define CHECK_NOSHUF(VA, SIZE) \ 94 #define CHECK_NOSHUF_PRED(GET_EA, SIZE, PRED) \ 521 #define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA) 528 #define fLOAD(NUM, SIZE, SIGN, EA, DST) \ 531 DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE(env, EA, GETPC()); \ 535 #define fMEMOP(NUM, SIZE, SIGN, EA, FNTYPE, VALUE) 549 #define fLOAD_LOCKED(NUM, SIZE, SIGN, EA, DST) \ 554 #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, insn->slot) 556 #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, slot) 560 #define fSTORE_LOCKED(NUM, SIZE, EA, SRC, PRED) \ [all …]
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H A D | gen_tcg_hvx.h | 424 #define fGEN_TCG_VEC_CMP(COND, TYPE, SIZE) \ argument 429 vec_to_qvec(SIZE, QdV_off, tmpoff); \ 453 #define fGEN_TCG_VEC_CMP_OP(COND, TYPE, SIZE, OP) \ argument 459 vec_to_qvec(SIZE, qoff, tmpoff); \
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/qemu/pc-bios/optionrom/ |
H A D | optionrom.h | 81 .macro read_fw_dma VAR, SIZE, ADDR 93 bswapl \SIZE 94 pushl \SIZE
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/qemu/hw/dma/ |
H A D | xlnx-zdma.c | 130 FIELD(ZDMA_CH_SRC_DSCR_WORD2, SIZE, 0, 30) 140 FIELD(ZDMA_CH_DST_DSCR_WORD2, SIZE, 0, 30) 401 SIZE); in zdma_write_dst() 405 SIZE); in zdma_write_dst() 439 SIZE, in zdma_write_dst() 456 src_size = FIELD_EX32(s->dsc_src.words[2], ZDMA_CH_SRC_DSCR_WORD2, SIZE); in zdma_process_descr() 483 SIZE); in zdma_process_descr()
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H A D | xlnx_csu_dma.c | 41 REG32(SIZE, 0x4) 42 FIELD(SIZE, SIZE, 2, 27) 43 FIELD(SIZE, LAST_WORD, 0, 1) /* rw, only exists in SRC */
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/qemu/target/hexagon/imported/ |
H A D | shift.idef | 97 #define ISHIFTTYPES(TAGEND,SIZE,REGD,REGS,REGSTYPE,ACC,ACCSRC,SAT,SATOPT,ATTRS) \ 98 Q6INSN(S2_asr_i_##TAGEND,#REGD "32" #ACC "=asr(" #REGS "32,#u" #SIZE ")" #SATOPT,ATTRIBS(ATTRS), \ 102 Q6INSN(S2_lsr_i_##TAGEND,#REGD "32" #ACC "=lsr(" #REGS "32,#u" #SIZE ")" #SATOPT,ATTRIBS(ATTRS), \ 114 #define ISHIFTTYPES_ONLY_ASL(TAGEND,SIZE,REGD,REGS,REGSTYPE,ACC,ACCSRC,SAT,SATOPT) \ 115 Q6INSN(S2_asl_i_##TAGEND,#REGD "32" #ACC "=asl(" #REGS "32,#u" #SIZE ")" #SATOPT,ATTRIBS(), \ 119 #define ISHIFTTYPES_ONLY_ASR(TAGEND,SIZE,REGD,REGS,REGSTYPE,ACC,ACCSRC,SAT,SATOPT) \ 120 Q6INSN(S2_asr_i_##TAGEND,#REGD "32" #ACC "=asr(" #REGS "32,#u" #SIZE ")" #SATOPT,ATTRIBS(), \ 125 #define ISHIFTTYPES_NOASR(TAGEND,SIZE,REGD,REGS,REGSTYPE,ACC,ACCSRC,SAT,SATOPT) \ 126 Q6INSN(S2_lsr_i_##TAGEND,#REGD "32" #ACC "=lsr(" #REGS "32,#u" #SIZE ")" #SATOPT,ATTRIBS(), \ 129 Q6INSN(S2_asl_i_##TAGEND,#REGD "32" #ACC "=asl(" #REGS "32,#u" #SIZE ")" #SATOPT,ATTRIBS(), \ [all …]
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H A D | macros.def | 1337 { DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE(thread,EA,insn); }, 1342 { memop##SIZE##_##FNTYPE(thread,EA,VALUE); }, 1367 { DST = (size##SIZE##SIGN##_t)mem_load_locked(thread,EA,SIZE,insn); }, 1372 { MEM_STORE##SIZE(thread,EA,SRC,insn); }, 1378 { PRED = (mem_store_conditional(thread,EA,SRC,SIZE,insn) ? 0xff : 0); },
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/qemu/hw/intc/ |
H A D | gicv3_internal.h | 286 FIELD(GITS_BASER, SIZE, 0, 8) 299 FIELD(GITS_CBASER, SIZE, 0, 8) 494 FIELD(DTE, SIZE, 1, 5)
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/qemu/include/hw/misc/ |
H A D | xlnx-versal-xramc.h | 73 FIELD(XRAM_IMP, SIZE, 0, 4)
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/qemu/target/ppc/ |
H A D | int_helper.c | 1691 #define ELEM_ADDR(VEC, IDX, SIZE) (&(VEC)->u8[IDX]) argument 1693 #define ELEM_ADDR(VEC, IDX, SIZE) (&(VEC)->u8[15 - (IDX)] - (SIZE) + 1) argument 1720 #define VEXTDVLX(NAME, SIZE) \ in VINSX() argument 1727 if (idx >= 0 && idx + SIZE <= sizeof(tmp)) { \ in VINSX() 1728 memcpy(&t->u8[ARRAY_SIZE(t->u8) / 2 - SIZE], (void *)tmp + idx, SIZE); \ in VINSX() 1732 env->nip, idx < 0 ? SIZE - idx : idx, 32 - SIZE); \ in VINSX() 1736 #define VEXTDVLX(NAME, SIZE) \ 1743 if (idx >= 0 && idx + SIZE <= sizeof(tmp)) { \ 1745 (void *)tmp + sizeof(tmp) - SIZE - idx, SIZE); \ 1749 env->nip, idx < 0 ? SIZE - idx : idx, 32 - SIZE); \
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