/qemu/hw/ssi/ |
H A D | ibex_spi_host.c | 54 REG32(STATUS, 0x14) 55 FIELD(STATUS, TXQD, 0, 8) 56 FIELD(STATUS, RXQD, 18, 8) 57 FIELD(STATUS, CMDQD, 16, 3) 58 FIELD(STATUS, RXWM, 20, 1) 60 FIELD(STATUS, RXSTALL, 23, 1) 62 FIELD(STATUS, RXFULL, 25, 1) 63 FIELD(STATUS, TXWM, 26, 1) 66 FIELD(STATUS, TXFULL, 29, 1) 67 FIELD(STATUS, ACTIVE, 30, 1) [all …]
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/qemu/hw/misc/ |
H A D | xlnx-versal-trng.c | 51 REG32(STATUS, 0x4) 52 FIELD(STATUS, QCNT, 9, 3) 53 FIELD(STATUS, EAT, 4, 5) 54 FIELD(STATUS, CERTF, 3, 1) 55 FIELD(STATUS, DTF, 1, 1) 56 FIELD(STATUS, DONE, 0, 1) 263 ARRAY_FIELD_DP32(s->regs, STATUS, QCNT, 4); in trng_regen() 355 ARRAY_FIELD_DP32(s->regs, STATUS, DONE, true); in trng_done() 368 if (FIELD_EX32(events, STATUS, CERTF)) { in trng_fault_event_set() 379 if (FIELD_EX32(events, STATUS, DTF)) { in trng_fault_event_set() [all …]
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/qemu/hw/nvram/ |
H A D | xlnx-versal-efuse-ctrl.c | 44 REG32(STATUS, 0x8) 45 FIELD(STATUS, AES_USER_KEY_1_CRC_PASS, 11, 1) 47 FIELD(STATUS, AES_USER_KEY_0_CRC_PASS, 9, 1) 48 FIELD(STATUS, AES_USER_KEY_0_CRC_DONE, 8, 1) 49 FIELD(STATUS, AES_CRC_PASS, 7, 1) 50 FIELD(STATUS, AES_CRC_DONE, 6, 1) 51 FIELD(STATUS, CACHE_DONE, 5, 1) 52 FIELD(STATUS, CACHE_LOAD, 4, 1) 53 FIELD(STATUS, EFUSE_2_TBIT, 2, 1) 54 FIELD(STATUS, EFUSE_1_TBIT, 1, 1) [all …]
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H A D | xlnx-zynqmp-efuse.c | 47 REG32(STATUS, 0x8) 48 FIELD(STATUS, AES_CRC_PASS, 7, 1) 49 FIELD(STATUS, AES_CRC_DONE, 6, 1) 50 FIELD(STATUS, CACHE_DONE, 5, 1) 51 FIELD(STATUS, CACHE_LOAD, 4, 1) 52 FIELD(STATUS, EFUSE_3_TBIT, 2, 1) 53 FIELD(STATUS, EFUSE_2_TBIT, 1, 1) 54 FIELD(STATUS, EFUSE_0_TBIT, 0, 1) 564 ARRAY_FIELD_DP32(s->regs, STATUS, AES_CRC_DONE, 1); in zynqmp_efuse_aes_crc_postw() 576 ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1); in zynqmp_efuse_cache_load_prew() [all …]
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/qemu/hw/dma/ |
H A D | xlnx-zynq-devcfg.c | 110 REG32(STATUS, 0x14) 111 FIELD(STATUS, DMA_CMD_Q_F, 31, 1) 112 FIELD(STATUS, DMA_CMD_Q_E, 30, 1) 113 FIELD(STATUS, DMA_DONE_CNT, 28, 2) 114 FIELD(STATUS, RX_FIFO_LVL, 20, 5) 115 FIELD(STATUS, TX_FIFO_LVL, 12, 7) 116 FIELD(STATUS, PSS_GTS_USR_B, 11, 1) 117 FIELD(STATUS, PSS_FST_CFG_B, 10, 1) 118 FIELD(STATUS, PSS_CFG_RESET_B, 5, 1)
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H A D | xlnx_csu_dma.c | 44 REG32(STATUS, 0x8) 45 FIELD(STATUS, DONE_CNT, 13, 3) /* wtc */ 46 FIELD(STATUS, FIFO_LEVEL, 5, 8) /* ro */ 47 FIELD(STATUS, OUTSTANDING, 1, 4) /* ro */ 48 FIELD(STATUS, BUSY, 0, 1) /* ro */ 147 cnt = ARRAY_FIELD_EX32(s->regs, STATUS, DONE_CNT) + a; in xlnx_csu_dma_update_done_cnt() 148 ARRAY_FIELD_DP32(s->regs, STATUS, DONE_CNT, cnt); in xlnx_csu_dma_update_done_cnt()
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/qemu/scripts/qemu-guest-agent/ |
H A D | fsfreeze-hook | 29 STATUS=$? 30 printf "$(date): $file finished with status=$STATUS\n" >>$LOGFILE
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/qemu/hw/char/ |
H A D | ibex_uart.c | 57 REG32(STATUS, 0x14) 58 FIELD(STATUS, TXFULL, 0, 1) 59 FIELD(STATUS, RXFULL, 1, 1) 60 FIELD(STATUS, TXEMPTY, 2, 1) 61 FIELD(STATUS, RXIDLE, 4, 1) 62 FIELD(STATUS, RXEMPTY, 5, 1)
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/qemu/hw/net/ |
H A D | e1000x_common.h | 80 mac[STATUS] &= ~E1000_STATUS_LU; in e1000x_update_regs_on_link_down() 89 mac[STATUS] |= E1000_STATUS_LU; in e1000x_update_regs_on_link_up()
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H A D | e1000x_common.c | 39 bool link_up = mac[STATUS] & E1000_STATUS_LU; in e1000x_rx_ready() 128 if (!(mac[STATUS] & E1000_STATUS_LU)) { in e1000x_hw_rx_enabled() 129 trace_e1000x_rx_link_down(mac[STATUS]); in e1000x_hw_rx_enabled()
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H A D | e1000.c | 256 [STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE | 813 uint32_t old_status = s->mac_reg[STATUS]; in e1000_set_link_status() 826 if (s->mac_reg[STATUS] != old_status) in e1000_set_link_status() 1135 getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS), 1396 nc->link_down = (s->mac_reg[STATUS] & E1000_STATUS_LU) == 0; in e1000_post_load() 1538 VMSTATE_UINT32(mac_reg[STATUS], E1000State),
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H A D | e1000_common.h | 37 defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH),
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H A D | e1000e_core.c | 1795 uint32_t old_status = core->mac[STATUS]; in e1000e_core_set_link_status() 1812 if (core->mac[STATUS] != old_status) { in e1000e_core_set_link_status() 1841 core->mac[STATUS] |= E1000_STATUS_PHYRA; in e1000e_set_ctrl() 2660 uint32_t res = core->mac[STATUS]; in e1000e_get_status() 3040 [STATUS] = e1000e_get_status, 3201 [STATUS] = e1000e_set_status, 3427 [STATUS] = E1000_STATUS_ASDV_1000 | E1000_STATUS_LU, 3524 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0; in e1000e_core_post_load()
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H A D | igb_common.h | 64 defreg(STATUS), defreg(SWSM), defreg(TCTL),
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H A D | igb_core.c | 2144 uint32_t old_status = core->mac[STATUS]; in igb_core_set_link_status() 2161 if (core->mac[STATUS] != old_status) { in igb_core_set_link_status() 2190 core->mac[STATUS] |= E1000_STATUS_PHYRA; in igb_set_ctrl() 2957 uint32_t res = core->mac[STATUS]; in igb_get_status() 3586 [STATUS] = igb_get_status, 4013 [STATUS] = igb_set_status, 4390 [STATUS] = E1000_STATUS_PHYRA | BIT(31), 4543 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0; in igb_core_post_load()
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H A D | trace-events | 114 e1000x_rx_link_down(uint32_t status_reg) "Received packet dropped because the link is down STATUS =…
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/qemu/include/hw/rtc/ |
H A D | xlnx-zynqmp-rtc.h | 65 FIELD(ADDR_ERROR, STATUS, 0, 1)
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/qemu/hw/acpi/ |
H A D | trace-events | 14 mhp_acpi_write_ost_status(uint32_t slot, uint32_t st) "slot[0x%"PRIx32"] OST STATUS: 0x%"PRIx32 41 cpuhp_acpi_write_ost_status(uint32_t slot, uint32_t st) "idx[0x%"PRIx32"] OST STATUS: 0x%"PRIx32
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/qemu/hw/scsi/ |
H A D | trace-events | 128 …int64_t mask, uint64_t status) "interrupt level set to %d (MASK: 0x%"PRIx64", STATUS: 0x%"PRIx64")"
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/qemu/target/mips/tcg/ |
H A D | msa_helper.c | 7429 #define NUMBER_QNAN_PAIR(ARG1, ARG2, BITS, STATUS) \ argument 7431 && float ## BITS ## _is_quiet_nan(ARG2, STATUS) 7447 #define FMAXMIN_A(F, G, X, _S, _T, BITS, STATUS) \ argument 7451 if (NUMBER_QNAN_PAIR(S, T, BITS, STATUS)) { \ 7454 else if (NUMBER_QNAN_PAIR(T, S, BITS, STATUS)) { \
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