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Searched refs:ARM_CPU_MODE_SVC (Results 1 – 7 of 7) sorted by relevance

/qemu/target/arm/
H A Dcpu.c364 env->uncached_cpsr = ARM_CPU_MODE_SVC; in arm_cpu_reset_hold()
659 ARM_CPU_MODE_SVC, in arm_emulate_firmware_reset()
661 ARM_CPU_MODE_SVC, in arm_emulate_firmware_reset()
H A Dinternals.h318 case ARM_CPU_MODE_SVC: in bank_number()
H A Dhelper.c10464 case ARM_CPU_MODE_SVC: in bad_mode_switch()
10917 if (mode == ARM_CPU_MODE_SVC) { in aarch64_sync_32_to_64()
10921 env->xregs[18] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)]; in aarch64_sync_32_to_64()
10922 env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; in aarch64_sync_32_to_64()
11027 if (mode == ARM_CPU_MODE_SVC) { in aarch64_sync_64_to_32()
11031 env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18]; in aarch64_sync_64_to_32()
11032 env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19]; in aarch64_sync_64_to_32()
11312 new_mode = ARM_CPU_MODE_SVC; in arm_cpu_do_interrupt_aarch32()
11459 case ARM_CPU_MODE_SVC: in aarch64_regnum()
11478 case ARM_CPU_MODE_SVC: in aarch64_regnum()
H A Dcpu.h1743 ARM_CPU_MODE_SVC = 0x13, enumerator
/qemu/target/arm/tcg/
H A Dhelper-a64.c727 case ARM_CPU_MODE_SVC: in el_from_spsr()
H A Dtranslate.c2726 *tgtmode = ARM_CPU_MODE_SVC; in msr_banked_access_decode()
2761 *tgtmode = ARM_CPU_MODE_SVC; in msr_banked_access_decode()
3411 case ARM_CPU_MODE_SVC: in gen_srs()
/qemu/hw/arm/
H A Dpxa2xx.c297 s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC; in pxa2xx_pwrmode_write()