/qemu/hw/tpm/ |
H A D | tpm_crb.c | 248 ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, in tpm_crb_reset() 250 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, in tpm_crb_reset() 252 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, in tpm_crb_reset() 254 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, in tpm_crb_reset() 256 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, in tpm_crb_reset() 258 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, in tpm_crb_reset() 260 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, in tpm_crb_reset() 262 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, in tpm_crb_reset() 264 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, in tpm_crb_reset() 266 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, in tpm_crb_reset() [all …]
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/qemu/hw/cxl/ |
H A D | cxl-component-utils.c | 239 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, DECODER_COUNT, in hdm_init_common() 244 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, in hdm_init_common() 246 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 3_6_12_WAY, 0); in hdm_init_common() 247 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 16_WAY, 0); in hdm_init_common() 248 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, UIO, 0); in hdm_init_common() 249 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, in hdm_init_common() 252 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, in hdm_init_common() 254 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_GLOBAL_CONTROL, in hdm_init_common() 311 ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ID, 1); in cxl_component_register_init_common() 312 ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, VERSION, in cxl_component_register_init_common() [all …]
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H A D | cxl-device-utils.c | 225 ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CTRL, in mailbox_reg_write() 360 ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP, in mailbox_reg_init_common() 364 ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP, in mailbox_reg_init_common() 366 ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP, in mailbox_reg_init_common() 369 ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP, in mailbox_reg_init_common() 371 ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP, in mailbox_reg_init_common()
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/qemu/hw/net/can/ |
H A D | xlnx-zynqmp-can.c | 332 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 1); in can_config_mode() 355 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 0); in update_status_register_mode_bits() 356 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 0); in update_status_register_mode_bits() 357 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 0); in update_status_register_mode_bits() 358 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 0); in update_status_register_mode_bits() 362 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 1); in update_status_register_mode_bits() 364 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 1); in update_status_register_mode_bits() 368 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 1); in update_status_register_mode_bits() 373 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 1); in update_status_register_mode_bits() 533 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, TXBFLL, 0); in transfer_fifo() [all …]
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H A D | xlnx-versal-canfd.c | 759 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 1); in canfd_config_mode() 788 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 0); in update_status_register_mode_bits() 789 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 0); in update_status_register_mode_bits() 790 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 0); in update_status_register_mode_bits() 791 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 0); in update_status_register_mode_bits() 795 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 1); in update_status_register_mode_bits() 797 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 1); in update_status_register_mode_bits() 811 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, ESTAT, 1); in update_status_register_mode_bits() 1415 ARRAY_FIELD_DP32(s->regs, SOFTWARE_RESET_REGISTER, CEN, in canfd_srr_pre_write() 1852 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, BBSY, 1); in canfd_xilinx_receive() [all …]
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/qemu/hw/dma/ |
H A D | xlnx-zdma.c | 247 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_STATUS, STATE, state); in zdma_set_state() 251 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_STATUS, STATE, 3); in zdma_set_state() 260 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_IRQ_SRC_ACCT, CNT, cnt); in zdma_src_done() 261 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, SRC_DSCR_DONE, true); in zdma_src_done() 275 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_IRQ_DST_ACCT, CNT, cnt); in zdma_dst_done() 276 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, DST_DSCR_DONE, true); in zdma_dst_done() 514 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, DMA_DONE, true); in zdma_process_descr() 521 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_CTRL2, EN, 0); in zdma_process_descr() 527 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, DMA_PAUSE, 1); in zdma_process_descr() 727 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true); in zdma_read() [all …]
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H A D | xlnx_csu_dma.c | 148 ARRAY_FIELD_DP32(s->regs, STATUS, DONE_CNT, cnt); in xlnx_csu_dma_update_done_cnt()
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/qemu/hw/nvram/ |
H A D | xlnx-zynqmp-efuse.c | 260 ARRAY_FIELD_DP32((s)->regs, reg, field, \ 436 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 0); in zynqmp_efuse_pgm_addr_postw() 440 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 1); in zynqmp_efuse_pgm_addr_postw() 446 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_DONE, 1); in zynqmp_efuse_pgm_addr_postw() 538 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 0); in zynqmp_efuse_rd_addr_postw() 539 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 1); in zynqmp_efuse_rd_addr_postw() 551 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 1); in zynqmp_efuse_rd_addr_postw() 552 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 0); in zynqmp_efuse_rd_addr_postw() 564 ARRAY_FIELD_DP32(s->regs, STATUS, AES_CRC_DONE, 1); in zynqmp_efuse_aes_crc_postw() 576 ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1); in zynqmp_efuse_cache_load_prew() [all …]
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H A D | xlnx-bbram.c | 155 ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, BBRAM_ZEROIZED, 0); in bbram_bdrv_sync() 173 ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, BBRAM_ZEROIZED, 1); in bbram_bdrv_zero() 226 ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, PGM_MODE, 1); in bbram_pgm_mode_postw() 252 ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, AES_CRC_PASS, in bbram_aes_crc_postw()
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H A D | xlnx-versal-efuse-ctrl.c | 459 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 1); in efuse_pgm_addr_postw() 462 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_DONE, 1); in efuse_pgm_addr_postw() 492 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 1); in efuse_rd_addr_postw() 495 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 1); in efuse_rd_addr_postw() 507 ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1); in efuse_cache_load_prew()
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/qemu/hw/i2c/ |
H A D | aspeed_i2c.c | 256 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, TX_LEN, 0); in aspeed_i2c_bus_send() 269 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, TX_LEN, in aspeed_i2c_bus_send() 317 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, RX_LEN, 0); in aspeed_i2c_bus_recv() 337 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, RX_LEN, in aspeed_i2c_bus_recv() 543 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_DONE, 1); in aspeed_i2c_bus_handle_cmd() 659 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN, RX_BUF_LEN, in aspeed_i2c_bus_new_write() 663 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN, TX_BUF_LEN, in aspeed_i2c_bus_new_write() 684 ARRAY_FIELD_DP32(bus->regs, I2CS_DMA_LEN, RX_BUF_LEN, in aspeed_i2c_bus_new_write() 1092 ARRAY_FIELD_DP32(bus->regs, I2CS_DMA_LEN_STS, RX_LEN, 0); in aspeed_i2c_bus_new_slave_event() 1100 ARRAY_FIELD_DP32(bus->regs, I2CS_INTR_STS, PKT_CMD_DONE, 1); in aspeed_i2c_bus_new_slave_event() [all …]
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/qemu/hw/misc/ |
H A D | xlnx-versal-trng.c | 263 ARRAY_FIELD_DP32(s->regs, STATUS, QCNT, 4); in trng_regen() 273 ARRAY_FIELD_DP32(s->regs, STATUS, QCNT, s->rand_count); in trng_rdout() 329 ARRAY_FIELD_DP32(s->regs, TRNG_ISR, CORE_INT, pending); in trng_core_int_update() 355 ARRAY_FIELD_DP32(s->regs, STATUS, DONE, true); in trng_done() 374 ARRAY_FIELD_DP32(s->regs, STATUS, CERTF, true); in trng_fault_event_set() 380 ARRAY_FIELD_DP32(s->regs, STATUS, DTF, true); in trng_fault_event_set() 394 ARRAY_FIELD_DP32(s->regs, TRNG_ISR, CORE_INT, 0); in trng_soft_reset()
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H A D | xlnx-versal-cframe-reg.c | 106 ARRAY_FIELD_DP32(s->regs, FAR0, BLOCKTYPE, blktype); in cframe_incr_far() 109 ARRAY_FIELD_DP32(s->regs, FAR0, FRAME_ADDR, faddr); in cframe_incr_far() 487 ARRAY_FIELD_DP32(s->regs, CMD0, CMD, pkt->data[0]); in cframe_reg_cfi_transfer_packet()
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H A D | xlnx-versal-cfu.c | 98 ARRAY_FIELD_DP32(s->regs, CFU_STATUS, SCAN_CLEAR_PASS, 1); in cfu_fgcr_postw() 99 ARRAY_FIELD_DP32(s->regs, CFU_STATUS, SCAN_CLEAR_DONE, 1); in cfu_fgcr_postw()
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H A D | xlnx-versal-xramc.c | 137 ARRAY_FIELD_DP32(s->regs, XRAM_IMP, SIZE, s->cfg.encoded_size); in xram_ctrl_reset_enter()
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/qemu/hw/ssi/ |
H A D | xlnx-versal-ospi.c | 394 ARRAY_FIELD_DP32(s->regs, FLASH_COMMAND_CTRL_MEM_REG, in ospi_stig_membank_req() 785 ARRAY_FIELD_DP32(s->regs, INDIRECT_READ_XFER_CTRL_REG, in ind_rd_inc_num_done() 791 ARRAY_FIELD_DP32(s->regs, INDIRECT_READ_XFER_CTRL_REG, in ospi_ind_rd_completed() 850 ARRAY_FIELD_DP32(s->regs, IRQ_STATUS_REG, in ospi_do_ind_read() 864 ARRAY_FIELD_DP32(s->regs, in ospi_do_ind_read() 941 ARRAY_FIELD_DP32(s->regs, INDIRECT_WRITE_XFER_CTRL_REG, in ind_wr_inc_num_done() 947 ARRAY_FIELD_DP32(s->regs, INDIRECT_WRITE_XFER_CTRL_REG, in ospi_ind_wr_completed() 1219 ARRAY_FIELD_DP32(s->regs, FLASH_COMMAND_CTRL_MEM_REG, in flash_cmd_ctrl_mem_reg_post_write() 1384 ARRAY_FIELD_DP32(s->regs, DLL_OBSERVABLE_UPPER_REG, in dll_obs_upper_reg_post_read() 1411 ARRAY_FIELD_DP32(s->regs, DLL_OBSERVABLE_LOWER_REG, in xlnx_versal_ospi_reset() [all …]
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/qemu/hw/pci-bridge/ |
H A D | pci_expander_bridge.c | 305 ARRAY_FIELD_DP32(reg_state, CXL_HDM_CAPABILITY_HEADER, ID, 0); in pxb_cxl_dev_reset() 307 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, in pxb_cxl_dev_reset()
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H A D | cxl_upstream.c | 93 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 8); in latch_registers()
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/qemu/include/hw/ |
H A D | registerfields.h | 152 #define ARRAY_FIELD_DP32(regs, reg, field, val) \ macro
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